Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (register, lsr, 64-bit)

Test 1: uops

Code:

  sub x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420351506110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351506110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351566110001735252000200010003257002035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351506110001735252000200010003257002035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351506110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351508410001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351606110001735252000200010003430412035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351566110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351506110001735252000200010003257012035203515753184210001000200020354211100110000731671117812000100020362036203620362036
100420351506110001735252000200010003257002035203515753184210001000200020354211100110000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  sub x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)18191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351490000126110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100021000710159111979120000101002003620036200362003620036
1020420035150000006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035150000006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035150000006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035149000006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035150000006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035150000006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035150000006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035150000036110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036
1020420035150000006110000198032520100201001010018534204916955200352003518429318700101001020020200200354211102011009910010100100000000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515060611000019743252001020010100101853101491695502003520035184513187181001010020200202003542111002110910100101000640463221979220000100102003620036200362003620036
100242003515060611000019743252001020010100101853101491695502003520035184513187181001010020204202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515007261000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853101491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515057611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515024611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
10024200351500611000019743252001020010100101853100491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515015611000019743252001020010100101853101491695502003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  sub x0, x1, x0, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150006110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500306110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150042910910000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500246110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150006110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150166110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500276110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500456110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
10204200351500061100001980325201002010010100185342491695520035200351842922187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200801501158861100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640663221979220000100102003620036200362003620036
1002420035150000124100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101010640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003514900061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036201742003620172
1002420035150000103100001974325200102003310010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
10024200351500270726100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
1002420035150024061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
10024200351500114061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
1002420035150084061100001974325200102001010010185310149169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  sub x0, x8, x9, lsr #17
  sub x1, x8, x9, lsr #17
  sub x2, x8, x9, lsr #17
  sub x3, x8, x9, lsr #17
  sub x4, x8, x9, lsr #17
  sub x5, x8, x9, lsr #17
  sub x6, x8, x9, lsr #17
  sub x7, x8, x9, lsr #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426748200000006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000000051103221126717160000801002672626726267262672626726
8020426725200000006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253941802011009910080100100000000051101221126717160000801002672626784267892672626726
8020426725200000008280000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000000051101221126717160000801002672626726267262672626726
8020426725200000006180000260942516010016010080100164318149236452672526725166153166778010080200160200267253911802011009910080100100000000051101221126717160000801002672626726267262672626726
8020426725200000006180000260942516010016010080100164318149236452672526725166153166778010080200160648267253911802011009910080100100000000051101221126717160000801002672626726267262672626726
8020426725200000006180000260942516010016010080100164318149236452672526725166243166778010080200160200267253911802011009910080100100000000051101221126717160000801002672626726267262672626726
8020426725200000006180000260942516010016010080100164318149236452672526725166153166778010080200160200269643911802011009910080100100000000051101551126717160000801002672626726267262672626726
8020426961200000006180000260942516048016010080100164318149236452672526725166153166778031980200160200267253911802011009910080100100000000051101221126717160000801002672626726267262696026726
802042672520000027606180000260942516010016010080100164318149236452684626789166153166778010080200160200267253911802011009910080100100000000051101221126717160000801002672626726267262672626726
80204267252000001206180000260942516010016010080100164318149236452684326822166153166778010080200160200267253911802011009910080100100000100051101221126717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242673520105100618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000005020162217926704160000800102671226712267122671226712
800242671120001800618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000005020722171726704160000800102671226712267122671226712
800242671120003300618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000005020172261726704160000800102671226712267122671226712
80024267112000000618000021280251600101600108001016314204923631267112677316623316685800108002016002026711391180021109108001010010005020172261726704160000800102671226712267122671226712
800242671120002400618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000005020172216526704160000800102671226712267122671226712
800242671120002400618000021280251600101600108001016314214923631267112671116623316685800108002016002026711391180021109108001010000005020172217826704160000800102671226712267122671226712
80024267112000240061800002128025160010160010800101631421492363126711267111662331668580010800201600202671139118002110910800101000000502062281726704160000800102671226712267122671226712
80024267112000000618000021280251600101600108001016314204923631267112671116623316685800108002016002026711391180021109108001010000005020722171726704160000800102671226712267122671226712
80024267111990150061800002128025160010160010800101631420492363126711267111662331668580010800201600202671139118002110910800101000600502062261726704160000800102671226712267122671226712
8002426711200030006180000212802516001016001080010163142049236312671126711166233166858001080020160020267113911800211091080010100000050201722171726704160000800102671226712267122671226712