Firestorm: STR (register, sxtw, 32-bit) measurements

Code:

  str w0, [x6, w7, sxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	554	4	0	0	3	1	0	0	528	16	16	1	25	1000	1000	1000	22884	542	542	355	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	544
1004	542	4	1	0	3	1	0	0	527	16	16	0	25	1000	1000	1000	22448	542	542	355	3	401	1000	1000	3000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	1	0	3	1	0	0	527	16	16	0	25	1000	1000	1000	23508	542	543	356	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	1	0	3	0	0	0	527	16	16	0	25	1000	1000	1000	23460	542	542	355	3	400	1000	1000	3000	542	554	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	544	544	544
1004	543	3	1	0	3	0	0	0	527	16	16	1	25	1000	1000	1000	23460	542	542	355	3	400	1000	1000	3000	542	554	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	1	0	3	0	0	0	528	16	16	0	25	1000	1000	1000	22448	543	542	355	3	400	1000	1000	3000	542	554	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	544	544	544	543	543
1004	542	4	1	0	3	1	0	0	528	16	16	0	25	1000	1000	1000	22956	542	542	355	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	1	0	3	1	0	0	527	16	16	1	25	1000	1000	1000	22908	542	542	355	3	412	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	555	543	543
1004	542	4	0	0	3	0	0	0	527	16	16	1	25	1000	1000	1000	22934	543	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	544	544	543	543	543
1004	542	4	1	0	3	1	0	0	527	16	16	0	25	1000	1000	1000	23438	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	555

Count: 8

Code:

  str w0, [x6, w7, sxtw]
  str w0, [x6, w7, sxtw]
  str w0, [x6, w7, sxtw]
  str w0, [x6, w7, sxtw]
  str w0, [x6, w7, sxtw]
  str w0, [x6, w7, sxtw]
  str w0, [x6, w7, sxtw]
  str w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40043	300	0	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839474	1	49	36960	40042	40040	29962	7	29994	80106	200	80016	200	240048	40043	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	80002	0	0	5	80002	2	42	1	1	1	5118	1	16	0	40040	1	80000	100	40043	40044	40044	40041	40041
80204	40042	300	0	0	3	1	0	40025	16	16	1	25	80100	100	80000	100	80006	500	1839503	1	49	36963	40040	40043	29961	7	29995	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	80002	1	0	2	80002	0	42	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40043	40043	40043	40041
80204	40042	300	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839474	1	49	36960	40042	40042	29959	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	80002	0	0	2	80000	2	42	1	1	1	5118	0	16	0	40039	0	80000	100	40041	40043	40043	40041	40043
80204	40042	299	0	0	3	1	0	40025	16	16	0	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40042	40042	29961	7	29994	80106	200	80016	200	240048	40046	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	80000	0	0	2	80002	2	42	1	1	1	5118	0	16	0	40040	0	80000	100	40044	40044	40043	40041	40043
80204	40042	300	0	6	3	1	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839618	1	49	36962	40040	40042	29961	7	29994	80107	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	80002	0	0	2	80002	2	42	1	1	1	5118	6	16	0	40040	0	80000	100	40041	40044	40041	40043	40043
80204	40042	300	0	0	3	1	0	40027	16	16	1	25	80100	100	80000	100	80006	500	1839378	1	49	36960	40054	40040	29961	7	29994	80106	200	80016	200	240048	40043	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	80002	0	0	2	80000	0	42	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40043	40044	40044	40041
80204	40040	299	0	0	3	0	0	40025	16	0	0	25	80100	100	80000	100	80006	500	1839474	1	49	36962	40042	40042	29961	7	29994	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	80002	0	0	2	80002	0	0	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40044	40044	40043	40041
80204	40040	300	0	0	0	0	0	40027	16	16	0	25	80100	100	80000	100	80006	500	1839474	1	49	36960	40042	40040	29959	7	29994	80107	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	80002	0	0	2	80000	2	42	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40043	40043	40043	40043
80204	40042	300	0	0	3	0	0	40025	16	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36963	40042	40042	29959	7	29992	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	80002	0	0	0	80000	0	42	1	1	1	5118	0	16	0	40039	0	80000	100	40043	40043	40044	40041	40044
80204	40040	300	0	0	3	0	0	40027	16	0	0	25	80100	100	80000	100	80006	500	1839378	1	49	36962	40040	40042	29961	7	29992	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	43	0	80002	0	0	0	80002	2	42	1	1	1	5118	0	16	0	40040	0	80000	100	40041	40044	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40059	300	0	0	0	0	0	0	147	6	1	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839424	49	36960	0	40040	40042	29978	3	30022	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80000	0	0	2	80000	2	34	0	5022	6	16	6	6	40039	0	80000	10	40051	40041	40050	40043	40050
80024	40042	299	0	0	0	0	0	1	228	3	1	0	0	40027	16	16	3	25	80010	10	80000	10	80000	50	1839832	49	36962	0	40040	40042	29985	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	8	80002	0	34	0	5020	6	16	6	4	40039	0	80000	10	40043	40043	40043	40041	40043
80024	40050	299	0	0	0	0	0	0	18	3	1	0	0	40035	16	16	0	25	80010	10	80000	10	80000	50	1839352	49	36962	3	40042	40042	29975	3	30020	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	0	80000	2	34	0	5020	6	16	4	6	40047	0	80000	10	40041	40051	40043	40041	40041
80024	40042	299	0	0	0	0	0	0	3	0	1	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839352	49	36962	0	40040	40042	29975	3	30020	80010	20	80000	20	240000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	2	80002	2	34	0	5020	6	16	6	6	40037	0	80000	10	40050	40043	40043	40043	40043
80024	40051	299	0	0	0	0	0	0	9	3	1	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	49	36960	0	40050	40042	29977	3	30022	80010	20	80000	20	240000	40042	40051	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80000	0	0	8	80000	2	34	0	5020	5	16	4	6	40037	0	80000	10	40041	40043	40041	40043	40043
80024	40040	300	0	0	0	0	0	0	6	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839808	49	36970	0	40042	40050	29977	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	2	80002	2	0	0	5020	6	16	6	6	40037	0	80000	10	40043	40041	40043	40051	40043
80024	40042	300	0	0	0	0	0	0	27	3	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	49	36960	0	40042	40050	29975	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	5	80002	0	34	0	5020	5	16	6	6	40039	0	80000	10	40043	40043	40043	40041	40041
80024	40050	300	0	0	0	0	0	0	12	3	1	0	0	40035	16	16	0	25	80010	10	80000	10	80000	50	1839424	49	36962	0	40042	40042	29975	3	30022	80010	20	80000	20	240000	40042	40049	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	0	5	80002	2	0	0	5020	4	16	4	6	40037	0	80000	10	40041	40043	40043	40043	40043
80024	40040	300	0	0	0	0	0	0	18	3	1	0	0	40035	16	16	0	25	80010	10	80000	10	80000	50	1839352	49	36962	0	40040	40040	29975	3	30030	80010	20	80000	20	240000	40050	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	80000	0	0	0	80002	2	0	0	5020	6	16	4	6	40037	0	80000	10	40041	40041	40043	40051	40043
80024	40050	300	0	0	0	0	0	0	6	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	49	36962	0	40042	40042	29978	3	30020	80010	20	80000	20	240000	40042	40050	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80000	0	0	5	80002	2	0	0	5020	4	16	6	4	40039	0	80000	10	40041	40043	40043	40041	40041

STR (register, sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations