Firestorm: TST (immediate, 64-bit) measurements

Code:

  tst x0, #3

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	41	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	57	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	1000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370

Test 2: Latency 2->1

Chain cycles: 1

Code:

  tst x0, #3
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	57	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17456	20100	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19928	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20067	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	149	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	149	495	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	21	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	21	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	536	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	6	17487	20112	20224	20224	20035	104	1	1	20201	100	99	100	20100	10100	0	1	1	1	1318	0	1	16	1	1	20011	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	149	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	3	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	82	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	199	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	174	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	191	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	82	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	145	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	20020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 3: throughput

Count: 8

Code:

  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26750	200	1	0	1	0	0	0	12	0	0	91	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80296	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	39	0	1	1	1	5118	3	16	1	1	26736	80015	100	26740	26740	26740	26740	26740
80204	26739	201	1	0	1	0	0	0	3	0	0	355	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80439	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	14	0	0	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26740	26740
80204	26878	200	1	0	1	0	0	0	117	0	0	49	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26876	26740
80204	26739	201	1	0	1	0	0	0	3	0	0	70	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	3	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26740	26740
80204	26739	201	1	0	1	0	0	0	111	0	0	239	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26740	26740
80204	26739	207	1	0	1	0	0	0	147	0	0	49	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80494	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	1	1	1	5118	2	16	1	2	26736	80015	100	26740	26740	26740	26740	26740
80204	26739	200	1	0	1	0	0	0	0	0	0	545	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	0	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26740	26740
80204	26739	201	1	0	1	0	0	0	3	0	0	278	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	57	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26740	26740
80204	26739	201	1	0	1	0	0	0	39	0	0	735	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	918	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26740	26740
80204	26739	200	1	0	1	0	0	0	0	0	0	70	27	80115	80115	80121	400590	1	49	23659	26739	26739	16679	6	16689	80121	80232	80232	26739	66	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	0	0	1	1	1	5118	1	16	1	1	26736	80015	100	26740	26740	26740	26740	26740

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	26722	200	0	0	35	25	80010	80010	80010	400050	0	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80064	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80265	80138	80010	400050	0	0	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	483	0	35	25	80010	80010	80010	400050	0	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	462	0	35	25	80010	80010	80010	400050	0	0	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	441	0	35	25	80010	80010	80010	400050	0	0	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	255	0	35	25	80010	80010	80010	400050	0	0	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5036	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	199	189	0	510	25	80010	80010	80010	400050	0	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	324	0	35	25	80010	80010	80010	400050	0	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	165	0	35	25	80010	80010	80010	400050	0	1	49	23625	26705	26705	16665	3	16683	80010	80020	80020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	0	0	2	18	0	0	2	2	26701	80000	0	10	26706	26706	26706	26706	26706

TST (immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations