Firestorm: LDP (64-bit) measurements

Code:

  ldp x0, x1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	402	3	1	1	0	1	0	0	67	1	0	2	387	2	7	7	19	25	1000	1000	1000	15559	402	403	101	3	136	1000	2000	1000	403	35	1	1	1001	0	1000	1000	1	1019	20	43	1060	0	0	0	60	1041	6	1	58	43	19	1	73	6	16	6	6	399	13	13	5	1000	1000	404	403	404	405	404
2004	402	3	1	1	0	0	0	0	66	1	0	3	387	3	9	7	19	25	1000	1000	1000	15575	403	402	100	3	136	1000	2000	1000	402	35	1	1	1001	0	1000	1000	0	1020	19	43	1059	1	1	2	64	1040	6	1	59	43	19	0	73	6	16	6	6	399	13	13	5	1000	1000	404	403	404	403	404
2004	403	3	1	1	0	0	0	0	69	1	0	2	388	3	7	7	19	25	1000	1000	1000	15535	403	403	100	3	136	1000	2000	1000	402	35	1	1	1001	0	1000	1000	1	1021	20	0	1059	0	1	1	60	1040	6	1	60	43	19	1	73	5	16	5	5	399	13	13	5	1000	1000	403	404	404	403	403
2004	402	3	1	1	1	0	1	0	67	1	0	3	388	2	7	7	18	25	1000	1000	1000	15550	402	403	100	3	135	1000	2000	1000	403	35	1	1	1001	0	1000	1000	0	1020	21	43	1059	1	0	0	61	1039	6	1	60	43	19	1	73	6	16	6	6	399	13	13	5	1000	1000	404	403	404	404	404
2004	402	3	1	1	1	0	0	0	66	1	0	3	387	3	7	7	20	25	1000	1000	1000	15538	403	403	101	3	136	1000	2000	1000	403	35	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	1	0	64	1040	6	1	59	43	19	1	73	5	16	6	6	400	13	13	5	1000	1000	403	404	403	404	404
2004	403	3	1	1	1	0	0	0	67	1	0	3	388	2	7	7	18	25	1000	1000	1000	15559	402	402	101	3	135	1000	2000	1000	403	35	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	0	1	63	1039	6	1	59	43	19	1	73	6	16	6	6	400	13	13	5	1000	1000	403	405	403	404	403
2004	402	3	1	1	1	0	0	0	67	1	0	3	389	3	7	7	20	25	1000	1000	1000	15535	403	403	100	3	136	1000	2000	1000	402	35	1	1	1001	0	1000	1000	0	1020	20	43	1059	1	0	1	64	1040	6	1	58	44	19	0	73	6	16	6	6	400	13	13	5	1000	1000	404	404	403	404	404
2004	403	2	1	1	0	0	0	0	67	1	0	2	387	2	7	7	19	25	1000	1000	1000	15554	403	403	100	3	135	1000	2000	1000	403	36	1	1	1001	0	1000	1000	0	1020	20	43	1059	0	1	0	64	1041	6	1	59	43	19	1	73	6	16	6	5	400	13	13	5	1000	1000	404	404	403	404	404
2004	403	3	1	0	0	0	0	0	76	1	0	2	387	3	7	7	19	25	1000	1000	1000	15521	402	402	100	3	135	1000	2000	1000	403	35	1	1	1001	0	1000	1000	0	1019	21	43	1058	1	1	1	64	1039	6	1	59	43	19	2	73	6	16	6	6	400	13	13	5	1000	1000	404	404	403	404	403
2004	402	3	1	0	0	0	0	0	66	1	0	3	388	3	7	7	20	25	1000	1000	1000	15559	402	402	101	3	136	1000	2000	1000	402	35	1	1	1001	0	1000	1000	0	1019	20	43	1060	0	1	0	61	1040	6	1	59	43	19	1	73	6	16	6	6	400	13	13	5	1000	1000	403	404	404	404	404

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70047	525	1	0	1	1	1	0	0	70057	69698	59700	25	40100	30103	10001	30100	10000	613915	3341304	49	66955	70047	70047	63403	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	3	10000	1	0	0	2610	2	64	1	1	69798	30003	9	6	0	10000	40100	70051	70036	70036	70051	70051
50204	70035	525	0	0	0	6	0	1	1	70035	69698	59684	25	40104	30100	10001	30100	10000	613915	3342056	49	66970	70047	70047	63400	3	63695	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	64	1	1	69813	30003	0	0	9	10000	40100	70051	70051	70051	70036	70048
50204	70050	525	0	0	0	1	0	1	0	70032	69714	59684	25	40104	30100	10001	30100	10000	613915	3342056	49	66955	70047	70050	63403	3	63707	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	10000	0	195	10000	0	1	0	2610	1	64	1	1	69813	30003	6	6	9	10000	40100	70036	70051	70051	70036	70051
50204	70050	525	0	0	0	0	0	0	1	70038	69698	59684	25	40104	30103	10001	30100	10000	613915	3341906	49	66970	70035	70047	63400	3	63710	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	0	2610	1	64	1	1	69813	30003	9	0	9	10000	40100	70051	70051	70051	70051	70051
50204	70050	525	0	0	0	48	0	0	0	70039	69714	59700	25	40100	30103	10001	30100	10000	613915	3342056	49	66970	70047	70050	63434	3	63695	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	0	10000	0	0	0	2610	1	64	1	2	70805	30000	9	6	0	10000	40100	70056	70056	70051	70036	70051
50204	70050	525	0	0	0	1	0	1	1	70035	69714	59700	25	40104	30100	10001	30100	10000	613915	3341304	49	66970	70050	70035	63403	3	63707	40100	30200	20000	60200	10000	70059	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	64	1	1	69813	30000	9	6	6	10000	40100	70051	70048	70051	70051	70051
50204	70050	524	0	0	1	1	0	1	1	70035	69714	59700	25	40100	30103	10001	30100	10000	613652	3342056	49	66970	70047	70035	63403	3	63695	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	1	1	0	2610	1	64	1	1	69798	30000	0	0	9	10000	40100	70051	70036	70036	70036	70051
50204	70035	525	0	0	0	0	0	0	1	70032	69698	59700	25	40100	30103	10001	30100	10000	613915	3341304	49	66970	70050	70050	63388	3	63710	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	2610	1	64	1	1	69813	30000	9	0	9	10000	40100	70036	70036	70051	70051	70036
50204	70043	525	0	0	0	1	0	0	1	70032	69714	59700	25	40104	30103	10001	30100	10000	613756	3342056	49	63994	70035	70050	63404	3	63695	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	64	1	1	69798	30003	9	0	6	10000	40100	70036	70051	70051	70048	70038
50204	70052	525	0	0	0	1	0	1	1	70098	69714	59700	25	40104	30100	10000	30100	10000	613652	3341304	49	66955	70035	70151	63403	3	63710	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	64	1	1	69813	30003	0	6	9	10000	40100	70048	70036	70051	70036	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	19	1e	1f	22	23	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70047	524	0	1	1	0	0	1	0	1	0	0	70059	69714	59692	25	40014	30013	10002	30010	10000	615126	3342046	1	49	66967	0	70050	70050	63446	3	63715	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2520	1	78	1	1	69801	30003	0	6	9	10000	40010	70051	70051	70051	70051	70051
50024	70047	524	0	0	0	0	0	1	0	0	0	0	70035	69719	59692	25	40014	30010	10001	30010	10000	615126	3342046	0	49	66970	0	70035	70050	63415	3	63683	40010	30020	20000	60020	10000	70035	37	2	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	1	78	1	1	69817	30000	0	6	9	10000	40010	70036	70036	70051	70036	70051
50024	70050	525	0	0	0	0	0	0	0	0	0	0	70020	69714	59677	25	40014	30010	10000	30010	10000	614994	3342046	0	49	66955	0	70035	70035	63403	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	1	78	1	3	69817	30003	9	6	0	10000	40010	70051	70051	70051	70036	70051
50024	70035	525	0	0	0	0	0	0	0	0	0	0	70020	69714	59692	25	40014	30013	10001	30010	10000	615126	3341536	0	49	66970	0	70050	70050	63418	3	63718	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	2520	3	78	1	1	69814	30003	9	6	9	10000	40010	70051	70036	70036	70051	70036
50024	70050	525	0	0	0	0	0	0	0	1	0	0	70035	69714	59692	25	40014	30010	10001	30010	10000	614994	3342046	0	49	66970	0	70050	70050	63415	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	1	0	10000	0	1	0	0	0	2520	1	78	1	1	69817	30000	9	0	9	10000	40010	70036	70051	70051	70051	70051
50024	70050	525	0	0	0	0	0	1	0	0	0	0	70069	69718	59677	25	40014	30010	10001	30010	10000	615126	3341295	0	49	66955	0	70050	70050	63418	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	1	78	1	3	69817	30003	0	9	0	10000	40010	70051	70051	70051	70051	70051
50024	70050	525	0	0	0	0	0	642	0	1	0	0	70032	69718	59689	25	40014	30013	10001	30010	10000	614994	3342046	0	49	66970	0	70050	70050	63418	3	63718	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	2520	1	78	1	3	69801	30003	6	0	9	10000	40010	70051	70051	70051	70051	70036
50024	70050	525	0	0	0	0	0	0	0	0	0	0	70032	69714	59692	25	40014	30013	10001	30010	10000	615126	3341295	0	49	66967	0	70050	70047	63403	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	2520	3	99	1	1	69817	30003	9	6	9	10000	40010	70036	70051	70051	70036	70036
50024	70035	525	0	0	0	0	0	0	0	0	0	0	70032	69714	59677	25	40010	30013	10001	30010	10000	614994	3341295	0	49	66955	0	70050	70047	63418	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	1	0	10000	1	1	0	0	0	2520	3	78	1	1	69817	30003	0	6	9	10000	40010	70036	70051	70051	70048	70051
50024	70035	525	0	0	1	1	0	0	0	1	0	0	70020	69719	59692	25	40014	30013	10001	30010	10000	615126	3342046	0	49	66955	0	70050	70035	63418	3	63682	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	2520	1	99	1	3	69817	30000	9	9	0	10000	40010	70051	70092	70113	70051	70053

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70057	525	1	1	1	0	0	2	1	0	0	70042	69827	59707	25	40108	30106	10002	30100	10000	613915	3341607	0	49	66977	0	70057	70057	63412	3	63687	40100	30200	20000	60200	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	1	10001	0	1	1	10000	1	1	0	1	0	2610	2	78	1	1	69851	30006	13	10	13	10000	40100	70058	70058	70061	70061	70042
50204	70060	524	1	1	1	1	1	2	1	0	0	70045	69725	59709	25	40108	30106	10001	30100	10000	613942	3342538	0	49	66980	3	70041	70060	63411	3	63720	40100	30200	20000	60200	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	3	0	10001	0	2	1	10000	0	1	1	1	1	2610	1	64	1	1	69860	30006	10	13	13	10000	40100	70042	70061	70061	70061	70042
50204	70060	524	1	0	1	0	0	2	0	0	0	70026	69725	59688	25	40104	30106	10002	30100	10000	613942	3342538	0	49	66980	0	70060	70060	63413	3	63720	40100	30200	20000	60200	10000	70057	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	1	1	10000	1	1	1	1	0	2610	1	64	1	1	69845	30003	0	13	13	10000	40100	70058	70061	70042	70061	70058
50204	70060	525	1	1	1	0	0	2	0	0	0	70045	69725	59688	25	40108	30103	10001	30100	10000	613942	3342538	1	49	66961	0	70060	70060	63413	3	63720	40100	30200	20000	60200	10000	70041	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	1	1	4	10000	1	1	0	1	0	2610	1	64	1	1	69866	30006	13	0	0	10000	40100	70061	70042	70061	70061	70042
50204	70057	525	1	0	0	0	0	7	0	0	1	70026	69722	59688	25	40108	30106	10002	30100	10000	613646	3342394	0	49	66961	0	70041	70060	63413	3	63720	40100	30200	20000	60200	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10005	0	1	1	10000	1	1	0	1	0	2610	1	64	1	1	69854	30006	0	13	13	10000	40100	70061	70042	70061	70061	70061
50204	70057	525	1	1	1	0	0	2	1	0	0	70045	69711	59706	25	40108	30103	10002	30100	10000	613942	3342394	0	49	66977	0	70060	70060	63410	3	63720	40100	30200	20000	60594	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10002	0	0	1	10000	1	1	1	1	1	2610	1	64	1	1	69867	30006	10	10	0	10000	40100	70058	70042	70058	70058	70058
50204	70060	524	1	0	1	0	0	2	0	0	1	70045	69722	59706	25	40104	30106	10002	30100	10000	613646	3345763	0	49	66980	0	70041	70060	63413	3	63720	40100	30200	20000	60200	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	0	10002	0	1	1	10000	1	1	1	1	1	2610	1	64	1	1	69882	30003	10	10	10	10000	40100	70058	70042	70058	70058	70058
50204	70057	524	1	0	1	0	0	2	0	0	0	70045	69725	59709	25	40108	30106	10001	30100	10000	613915	3342394	0	49	66961	0	70060	70041	63413	3	63720	40100	30200	20000	60200	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10003	0	0	1	10000	1	1	1	1	0	2610	1	64	1	1	69867	30006	0	13	10	10000	40100	70058	70042	70061	70042	70061
50204	70057	525	1	1	0	0	0	2	0	0	0	70045	69725	59688	25	40104	30106	10002	30100	10000	613942	3342538	1	49	66961	0	70060	70060	63413	3	63720	40100	30200	20000	60200	10000	70060	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	0	1	1	10000	0	1	1	1	1	2610	1	78	1	1	69891	30006	13	13	13	10000	40100	70061	70061	70061	70042	70042
50204	70060	524	1	0	0	1	1	1	0	0	0	70045	69711	59709	25	40108	30106	10002	30100	10000	613942	3342538	1	49	66977	0	70041	70041	63410	3	63717	40100	30200	20000	60572	10000	70057	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10002	0	0	1	10000	1	1	1	1	0	2610	1	64	1	2	69880	30006	0	10	10	10000	40100	70061	70042	70061	70042	70061

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70047	524	0	1	0	0	0	1	0	1	0	70020	69714	59689	25	40014	30013	10001	30010	10000	615102	3341295	1	49	66955	0	70047	70047	63415	3	63715	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	1	0	10000	1	1	0	0	2520	5	78	3	4	69801	30003	6	6	6	10000	40010	70048	70036	70048	70048	70048
50024	70050	525	0	0	0	0	0	1	0	0	0	70032	69714	59692	25	40014	30013	10000	30010	10000	614994	3341899	1	49	66970	0	70050	70035	63418	3	63715	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	1	0	10000	1	1	0	0	2520	4	78	3	6	69817	30003	9	9	0	10000	40010	70051	70036	70048	70051	70051
50024	70035	525	0	0	0	0	0	9	0	0	0	70020	69714	59692	25	40014	30010	10001	30010	10000	615126	3342046	1	49	66970	0	70035	70047	63415	3	63715	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	0	0	0	2520	4	78	4	4	69817	30003	0	6	9	10000	40010	70036	70051	70051	70051	70036
50025	70050	524	0	0	0	0	0	1	0	1	0	70032	69719	59708	25	40010	30013	10001	30010	10000	615126	3342094	1	49	66955	0	70050	70035	63418	3	63682	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	0	0	2520	5	99	4	3	69817	30000	9	6	6	10000	40010	70048	70048	70036	70048	70051
50024	70035	525	0	0	0	0	0	0	0	0	0	70020	69718	59677	25	40014	30010	10001	30010	10000	615102	3341295	1	49	66970	0	70047	70035	63415	3	63718	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	1	0	0	2520	5	78	4	4	69814	30003	0	9	0	10000	40010	70036	70051	70048	70048	70036
50024	70047	525	0	1	0	0	0	1	0	1	0	70035	69714	59677	25	40014	30013	10000	30010	10000	615102	3342046	1	49	66970	0	70035	70047	63403	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	1	3	10000	0	0	0	0	2520	3	99	3	4	69817	30003	0	9	9	10000	40010	70051	70048	70048	70051	70036
50024	70035	525	0	0	0	0	0	1	0	0	0	70020	69714	59692	25	40010	30013	10000	30010	10000	615102	3341899	1	49	66970	0	70050	70035	63418	3	63715	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	0	0	0	0	2520	5	99	5	5	69814	30003	9	6	0	10000	40010	70051	70036	70051	70048	70048
50024	70047	524	0	0	0	0	0	1	0	1	0	70035	69714	59677	25	40014	30010	10001	30010	10000	615126	3342046	1	49	66970	0	70035	70047	63480	3	63682	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	0	0	2520	2	99	2	4	69817	30003	9	6	6	10000	40010	70051	70051	70036	70048	70051
50024	70050	525	0	1	0	0	0	1	0	1	0	70035	69719	59692	25	40014	30013	10001	30010	10000	615126	3342046	1	49	66970	0	70050	70050	63418	3	63682	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	0	1	0	0	2520	6	78	4	4	69817	30003	9	9	9	10000	40010	70054	70052	70051	70051	70054
50024	70050	525	0	1	0	1	0	1	0	0	0	70035	69718	59692	25	40010	30013	10001	30010	10000	615021	3341899	1	49	66970	0	70050	70050	63418	3	63775	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	0	0	0	2520	4	78	3	5	69814	30013	0	6	0	10000	40010	70342	70126	70036	70053	70051

Test 4: throughput

Count: 8

Code:

  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]
  ldp x0, x1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26726	200	1	0	0	0	0	0	0	0	0	0	0	1	0	0	26707	2	18	18	0	25	80100	100	80000	100	80000	500	1168880	1	49	23642	26722	26722	6645	0	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	35	80000	6	1	35	39	5110	2	16	2	2	26726	0	6	0	2	80000	80100	26708	26723	26723	26708	26708
160204	26722	200	0	0	0	0	0	1	1	0	0	41	0	1	0	1	26707	0	18	0	12	25	80100	100	80000	100	80000	500	1175837	1	49	23642	26707	26722	6645	0	3	6665	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	0	80035	0	0	0	39	5110	2	16	2	2	26720	0	6	6	2	80000	80100	26723	26723	26708	26723	26723
160204	26727	200	0	0	0	0	0	0	0	0	0	0	0	1	0	1	26692	2	18	12	12	25	80100	100	80000	100	80000	500	1168880	1	49	23642	26722	26722	6645	0	3	6665	80100	200	160000	200	80000	26727	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	0	80035	0	1	0	43	5110	2	16	2	2	26728	0	0	6	2	80000	80100	26708	26708	26708	26723	26723
160204	26707	200	0	0	0	0	0	0	0	0	0	0	0	1	0	1	26707	2	0	0	16	25	80100	100	80000	100	80000	500	1170107	0	49	23642	26722	26722	6645	0	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80035	0	0	0	35	80035	6	0	36	39	5110	2	16	2	3	26735	0	0	6	2	80000	80100	26723	26723	26708	26723	26723
160204	26722	199	0	0	0	0	0	0	0	0	0	41	0	1	0	1	26707	2	0	0	12	25	80231	100	80130	102	80000	500	1175359	1	49	23627	26722	26722	6645	0	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	2	39	31	80035	0	1	0	35	80000	6	1	0	39	5110	2	16	2	2	26726	0	6	6	2	80000	80100	26723	26723	26723	26711	26723
160204	26707	200	0	0	0	0	0	0	0	0	0	53	0	0	0	0	27334	0	12	18	12	25	80100	100	80000	100	80000	500	1170107	1	49	23644	26707	26722	6630	0	3	6670	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80000	0	2	0	38	80390	0	1	35	39	5110	2	16	2	2	26708	0	0	6	0	80000	80100	26723	26708	26723	26723	26723
160204	26707	200	0	0	0	0	0	0	0	0	0	0	0	0	0	1	26710	2	12	0	12	25	80100	100	80000	100	80000	500	1170107	0	49	23647	26722	26707	6645	0	3	6665	80100	200	160000	200	80173	26727	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	3	80035	6	1	35	0	5110	2	16	2	2	26707	0	6	0	2	80000	80100	26708	26726	26728	26708	26723
160204	26722	200	0	0	0	0	0	0	0	0	0	41	0	1	0	0	26692	2	0	18	12	25	80100	100	80000	100	80000	500	1168880	0	49	23642	26727	26722	6645	0	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80036	0	0	0	0	80035	6	1	35	0	5110	2	16	2	2	26728	0	0	6	2	80000	80100	26708	26708	26708	26723	26728
160204	26722	200	0	0	0	0	0	0	0	0	0	41	0	0	0	1	26692	2	18	0	11	25	80100	100	80000	100	80000	500	1170107	1	49	23642	26727	26707	6645	0	3	6665	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	0	80035	6	1	35	39	5110	2	16	2	2	26724	0	10	0	2	80000	80100	26723	26723	26723	26723	26723
160204	26707	200	0	0	0	0	0	1	0	0	0	41	0	0	0	0	26712	0	18	18	3	25	80100	100	80000	100	80000	500	1167520	0	49	23642	26722	26722	6645	0	3	6680	80100	200	160000	200	80000	26722	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80000	0	0	0	39	80039	0	0	35	39	5110	2	16	2	2	26719	0	0	10	2	80000	80100	26723	26723	26723	26723	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26733	201	1	1	1	0	1	0	0	0	65	1	0	0	26696	2	12	18	16	25	80010	10	80000	10	80000	50	1168880	49	23627	26708	26732	6653	3	6707	80010	20	160000	20	80000	26792	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	1	0	39	80039	6	1	0	39	0	0	5020	0	1	16	1	1	26719	10	6	4	80000	80010	26728	26728	26708	26728	26728
160024	26722	200	0	0	0	0	0	0	0	0	45	1	0	1	26692	2	0	18	12	25	80010	10	80000	10	80000	50	1170107	49	23647	26730	26727	6672	3	6702	80010	20	160000	20	80000	26758	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80039	0	0	0	39	80039	6	0	0	0	0	0	5020	0	1	16	1	1	26704	10	0	4	80000	80010	26708	26728	26708	26728	26728
160024	26727	200	0	0	0	0	0	0	0	0	45	0	0	0	26712	0	12	12	16	25	80142	10	80000	10	80000	50	1168880	49	23627	26727	26707	6653	3	6707	80010	20	160000	20	80000	26768	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80035	0	0	0	0	80039	6	1	35	39	0	0	5020	0	1	16	1	1	26724	0	10	0	80000	80010	26728	26723	26728	26728	26728
160024	26707	200	0	0	0	0	0	0	0	0	0	1	0	0	26712	0	12	12	16	25	80010	10	80000	10	80000	50	1168754	49	23627	26727	26727	6672	3	6687	80010	20	160000	20	80000	26719	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	0	0	0	39	80040	0	1	39	43	0	0	5020	0	1	16	1	1	26724	10	10	0	80000	80010	26708	26723	26723	26723	26728
160024	26707	200	0	0	0	0	0	0	0	0	45	1	0	0	26712	0	0	12	16	25	80010	10	80000	10	80000	50	1170107	49	23647	26707	26722	6653	3	6687	80010	20	160000	20	80000	26863	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80039	0	0	0	35	80039	6	1	0	43	0	0	5020	0	1	16	1	1	26704	4	6	0	80000	80010	26728	26728	26708	26708	26728
160024	26727	200	0	0	0	0	0	0	0	0	41	1	0	2	26692	0	0	12	16	25	80010	10	80000	10	80000	50	1174628	49	23647	26727	26727	6673	3	6687	80010	20	160000	20	80000	26732	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	0	39	80039	6	1	39	43	0	0	5020	0	1	16	1	1	26724	0	4	4	80000	80010	26827	26728	26728	26728	26728
160024	26727	200	0	0	0	0	0	0	0	0	0	0	0	2	26712	2	12	0	16	25	80010	10	80000	10	80000	50	1174628	49	23647	26727	26727	6653	3	6702	80010	20	160000	20	80000	26737	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80000	0	0	0	0	80039	6	1	39	39	0	0	5020	0	1	16	1	1	26723	0	10	0	80000	80010	26708	26728	26728	26726	26708
160024	26722	200	0	0	0	0	0	0	0	0	45	0	0	0	26714	2	12	0	16	25	80010	10	80000	10	80000	50	1173183	49	23647	26727	26727	6672	3	6707	80010	20	160354	20	80000	26732	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80035	0	1	0	0	80035	0	1	40	0	0	0	5020	0	1	16	1	1	26704	10	10	4	80000	80010	26728	26708	26728	26708	26728
160024	26707	200	0	0	0	0	0	0	0	0	45	1	0	2	26692	2	12	0	16	25	80010	10	80000	10	80000	50	1173183	49	23627	26727	26727	6653	3	6687	80010	20	160000	20	80000	26719	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	0	0	0	0	80039	6	1	0	0	0	0	5020	0	1	16	1	1	26719	0	10	0	80000	80010	26723	26728	26728	26723	26708
160024	26727	200	0	0	0	0	1	0	0	0	45	0	0	0	26692	0	18	18	16	25	80010	10	80000	10	80000	50	1168754	49	23647	26707	26727	6672	3	6702	80010	20	160000	20	80000	26745	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	0	80000	0	0	0	54	80039	6	0	39	43	0	0	5020	0	1	16	1	1	26724	10	10	0	80000	80010	26723	26708	26728	26723	26728

LDP (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations