Firestorm: LDRSH (register, uxtw, 64-bit) measurements

Code:

  ldrsh x0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	2	0	0	45	1	0	0	379	2	12	12	16	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	3	2	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15037	1	398	398	221	3	256	1000	1000	2000	394	81	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	6	1	39	44	73	1	16	2	2	395	14	14	7	1000	399	395	399	399	399
1004	398	2	0	0	44	1	0	1	383	3	1	1	19	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	44	1038	0	39	1039	6	1	38	44	73	1	16	2	2	396	14	14	4	1000	399	399	401	395	399
1004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	6	1	39	44	73	1	16	2	1	397	14	14	7	1000	400	399	399	399	399
1004	398	3	0	0	44	0	0	1	379	2	12	1	19	25	1000	1000	1000	14989	1	398	394	221	3	252	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	2	1	398	14	14	7	1000	402	399	399	399	399
1004	398	2	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15037	1	394	394	217	3	252	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	43	73	1	16	2	2	395	10	10	7	1000	401	399	399	399	399
1004	398	2	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	43	73	1	16	2	2	395	14	10	4	1000	395	399	399	399	399
1004	394	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	2	2	391	14	10	7	1000	395	399	399	399	395
1004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	6	1	39	44	73	1	16	2	2	391	14	14	7	1000	417	399	399	399	399
1004	398	3	0	0	44	0	0	1	390	2	1	1	19	25	1000	1000	1000	15208	1	398	398	221	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	39	1039	6	1	40	44	73	1	16	1	1	391	14	14	7	1000	399	399	399	399	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0048

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	0	0	0	0	0	1	0	1	0	70020	69764	59709	25	40104	30103	10000	30100	10000	616005	3342206	49	66970	70050	70050	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69798	30003	9	6	0	10000	30100	70036	70051	70036	70048	70051
40204	70047	524	0	0	0	0	0	0	1	0	1	0	70035	69764	59695	25	40100	30103	10001	30100	10000	616005	3342206	49	66970	70050	70035	64643	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	0	1	10000	0	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69813	30000	9	9	9	10000	30100	70051	70051	70048	70051	70051
40204	70050	524	0	0	0	0	0	0	1	0	1	0	70035	69781	59706	25	40104	30103	10001	30100	10000	616175	3342206	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	2	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69813	30003	9	9	9	10000	30100	70051	70051	70036	70051	70049
40204	70035	525	0	0	0	0	0	0	0	0	1	0	70035	69735	59720	25	40104	30100	10001	30100	10000	616175	3342206	49	66970	70050	70047	64646	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	0	3	10000	1	1	0	0	0	2610	1	71	1	1	69810	30000	9	9	0	10000	30100	70051	70048	70051	70036	70053
40204	70088	525	0	0	0	0	0	0	1	0	0	0	70020	69781	59709	25	40104	30103	10000	30100	10000	616005	3341470	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	0	3	10000	1	0	0	0	0	2610	1	71	1	1	69798	30003	9	9	0	10000	30100	70036	70036	70051	70051	70417
40204	70050	524	0	0	0	0	0	0	1	0	0	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616175	3342206	49	66967	70050	70035	64646	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	2	0	18	10000	1	1	0	0	0	2610	1	71	1	1	69813	30003	6	6	0	10000	30100	70048	70051	70051	70048	70054
40204	70035	524	0	0	0	0	0	0	1	0	0	0	70035	69781	59709	25	40100	30103	10001	30100	10000	616005	3342206	49	66955	70050	70050	64646	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69813	30000	9	9	9	10000	30100	70051	70036	70048	70051	70060
40204	70050	525	0	0	0	0	0	0	1	0	0	0	70035	69735	59706	25	40104	30103	10001	30100	10000	616005	3342062	49	66955	70050	70047	64643	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	0	2610	1	71	1	1	69798	30000	9	0	9	10000	30100	70051	70051	70036	70048	70039
40204	70035	525	0	0	0	0	0	0	0	0	1	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616005	3342062	49	66970	70050	70050	64646	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	3	0	0	10000	0	0	0	0	0	2610	1	71	1	1	69813	30003	9	0	0	10000	30100	70051	70051	70051	70036	70052
40204	70047	525	0	0	0	0	0	0	0	0	1	0	70032	69781	59709	25	40100	30103	10000	30100	10000	616175	3342206	49	66970	70050	70050	64643	3	64938	40100	30200	10000	60200	20000	70035	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10000	0	1	0	0	0	2610	1	71	1	1	69813	30000	6	9	0	10000	30100	70051	70036	70051	70051	70072

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	0	1	1	0	0	1	0	70032	69728	59709	25	40014	30010	10001	30010	10000	616952	3342062	0	0	49	66955	70035	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	1	2520	1	71	0	1	1	69798	30003	6	6	6	10000	30010	70048	70048	70048	70051	70051
40024	70047	524	1	0	1	1	1	0	1	0	70032	69743	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	0	49	66970	70047	70047	64665	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	0	1	1	69810	30003	9	6	6	10000	30010	70051	70036	70048	70036	70048
40024	70035	525	0	0	0	1	1	0	1	0	70032	69760	59709	25	40014	30013	10001	30010	10000	616982	3342206	0	0	49	62799	70035	70047	64665	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	3	0	10000	1	1	0	2520	1	71	0	1	1	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70049
40024	70047	524	0	0	1	1	1	0	0	0	70032	69760	59706	25	40014	30013	10001	30010	10000	616952	3342206	1	0	49	66970	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	0	1	1	69810	30003	6	6	9	10000	30010	70051	70051	70048	70051	70051
40024	70050	525	1	0	0	0	1	0	1	0	70035	69728	59695	25	40014	30013	10001	30010	10000	616952	3342062	0	0	49	66955	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	0	1	1	69810	30000	6	6	0	10000	30010	70048	70048	70048	70048	70036
40024	70047	525	1	0	0	0	1	0	1	0	70035	69728	59706	25	40014	30010	10000	30010	10000	617068	3341470	1	0	49	66967	70047	70035	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	2520	1	71	0	1	1	69813	30003	9	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70035	525	0	0	0	0	1	0	0	0	70035	69760	59709	25	40014	30013	10001	30010	10000	616982	3342062	0	0	49	66970	70035	70035	64665	3	64972	40010	30020	10000	60020	20000	70047	82	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	2520	1	71	0	1	1	69810	30000	6	6	6	10000	30010	70048	70048	70051	70048	70048
40024	70047	525	0	0	0	0	1	0	1	0	70020	69728	59706	25	40014	30013	10000	30010	10000	618170	3342062	0	0	49	66967	70035	70050	64668	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	0	1	1	69810	30003	9	0	0	10000	30010	70055	70051	70048	70048	70051
40024	70047	524	0	0	0	0	0	0	1	0	70020	69734	59707	36	40014	30013	10001	30010	10000	617000	3342206	0	0	49	66955	70047	70050	64668	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	2520	1	71	0	2	2	69810	30003	6	6	6	10000	30010	70051	70051	70048	70051	70051
40024	70047	525	0	0	0	0	1	0	1	0	70032	69760	59717	25	40014	30010	10001	30010	10000	616982	3342206	0	0	49	66967	70050	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	0	1	1	69798	30003	6	6	6	10000	30010	70036	70048	70048	70048	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	1	0	0	0	0	1	0	1	0	70035	69772	59718	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66970	0	70049	70050	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	2610	1	71	1	1	69813	30003	9	6	9	10000	30100	70051	70048	70115	70064	70049
40204	70047	524	0	0	0	0	0	1	0	0	0	70020	69741	59709	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66955	0	70050	70047	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69810	30003	9	9	9	10000	30100	70051	70048	70142	70115	70036
40204	70050	525	0	0	0	0	0	1	0	1	0	70101	69867	59712	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66955	0	70050	70050	64643	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69813	30003	9	6	9	10000	30100	70048	70048	70131	70051	70051
40204	70050	525	0	0	0	0	0	1	0	1	0	70035	69769	59709	25	40108	30103	10001	30100	10000	616005	3342206	1	49	66970	0	70050	70050	64643	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	1	10000	0	1	0	2610	1	71	1	1	69813	30003	9	9	0	10000	30100	70051	70048	70114	70075	70048
40204	70047	525	0	0	0	0	0	0	0	0	1	70035	69865	59696	25	40104	30103	10001	30100	10000	616015	3342939	1	49	66970	0	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69813	30003	6	6	9	10000	30100	70051	70048	70140	70092	70051
40204	70050	524	0	0	0	0	0	0	0	0	0	70035	69802	59710	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66970	0	70050	70047	64646	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69813	30003	6	0	9	10000	30100	70051	70051	70156	70062	70056
40204	70047	525	0	1	0	0	0	1	0	0	0	70035	69794	59707	25	40104	30103	10001	30100	10000	616015	3342206	1	49	66967	0	70050	70050	64646	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69810	30003	9	6	6	10000	30100	70051	70048	70149	70084	70051
40204	70050	525	0	0	0	0	0	1	0	0	1	70035	69887	59711	25	40104	30103	10000	30100	10000	616005	3342206	1	49	66970	0	70050	70050	64646	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10001	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69813	30000	9	0	9	10000	30100	70051	70051	70051	70105	70051
40204	70047	525	0	0	0	0	0	514	0	0	1	70050	69775	59711	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66970	0	70050	70047	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	1	0	2610	1	71	1	1	69813	30003	9	0	9	10000	30100	70051	70048	70127	70108	70051
40204	70050	525	0	0	0	0	0	0	0	0	0	70035	69838	59710	25	40100	30103	10001	30100	10000	616015	3342206	1	49	66970	0	70050	70035	64646	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	2610	1	71	1	1	69798	30003	6	0	9	10000	30100	70051	70048	70128	70106	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	1	0	0	0	0	0	0	1	0	0	0	70032	69728	59706	25	40010	30013	10002	30010	10000	617068	3342062	49	66967	70047	70035	64653	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	6	0	38656	10048	1	1	0	2920	15	211	10	11	70993	30168	6	0	6	10000	30010	71502	71590	71603	71544	71580
40024	71536	537	6	1	1	0	0	0	0	18	17	2311	1496	1	0	70032	69728	59706	25	40014	30010	10001	30010	10000	617068	3344722	49	66967	70328	70499	65088	132	65759	43129	32563	10824	65252	20988	71494	35	18	1	40021	10	9	10	10000	30010	10000	0	10	10057	0	1	10035	1	0	38503	10054	1	1	2	3067	7	190	11	17	71388	30217	0	0	6	10000	30010	71698	71966	71872	71868	70036
40024	70035	524	0	0	0	0	0	0	0	0	2	1198	1232	1	0	70020	69730	59706	25	40200	30165	10047	31873	10663	650087	3375624	49	66967	70037	70047	64665	141	65860	42739	30020	10000	60020	20438	70038	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	58	0	0	10000	0	0	0	2520	5	71	5	7	69898	30003	6	0	6	10000	30010	70048	70036	70048	70048	70052
40024	70051	525	0	0	0	0	0	0	1	0	0	0	0	0	0	70032	69743	59728	25	40010	30010	10001	30010	10000	616952	3342062	49	66959	70035	70035	64653	3	64960	40010	30020	10000	60020	20000	70140	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	0	10000	0	0	0	10000	1	1	0	2520	7	71	5	7	69923	30000	6	6	0	10000	30010	70048	70048	70036	70048	70112
40024	70047	525	0	0	0	0	0	0	0	0	0	1	0	1	0	70020	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	49	66970	70050	70035	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	2	0	6	10000	1	1	0	2520	5	71	5	7	69801	30000	0	6	6	10000	30010	70048	70048	70048	70036	70079
40024	70047	524	0	0	0	0	0	0	0	0	0	1	0	1	0	70032	69728	59797	25	40014	30010	10001	30010	10000	617068	3342062	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	55	0	0	10000	1	1	0	2520	5	71	7	5	69810	30000	6	6	6	10000	30010	70139	70048	70051	70048	70084
40024	70051	525	0	0	0	0	0	1	0	0	0	1	0	1	0	70032	69728	59706	25	40014	30010	10001	30010	10000	616952	3341854	49	66967	70047	70047	64665	3	64960	40206	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	35	0	0	10000	1	0	0	2520	7	71	5	7	69798	30003	6	0	0	10000	30010	70048	70048	70048	70049	70105
40024	70035	525	0	0	0	0	0	0	0	0	0	0	0	0	0	70032	69728	59712	25	40010	30013	10000	30010	10000	616952	3342062	49	66967	70035	70055	64653	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10006	40	0	0	10000	1	1	0	2520	7	71	7	5	69798	30000	6	0	6	10000	30010	70036	70048	70036	70048	70089
40024	70047	524	0	0	0	0	0	0	0	0	0	27	0	0	0	70020	69743	59712	25	40014	30010	10001	30010	10000	617068	3342062	49	66957	70053	70047	64666	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	57	0	0	10000	0	1	0	2520	5	71	5	7	69798	30003	6	0	6	10000	30010	70048	70036	70036	70036	70093
40024	70035	524	0	0	0	0	0	0	1	0	0	1	0	1	0	70032	69743	59712	25	40014	30010	10001	30010	10000	617068	3342062	49	66955	70047	70035	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	3	2	111	10000	1	0	0	2520	7	71	5	7	69798	30003	6	6	6	10000	30010	70048	70048	70036	70048	70107

Test 4: throughput

Count: 8

Code:

  ldrsh x0, [x6, w7, uxtw]
  ldrsh x0, [x6, w7, uxtw]
  ldrsh x0, [x6, w7, uxtw]
  ldrsh x0, [x6, w7, uxtw]
  ldrsh x0, [x6, w7, uxtw]
  ldrsh x0, [x6, w7, uxtw]
  ldrsh x0, [x6, w7, uxtw]
  ldrsh x0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26727	200	0	0	0	0	1	45	1	3	26721	2	7	7	27	25	80100	100	80000	100	80016	500	1166596	0	49	23647	26727	26727	16655	6	16693	80115	200	80024	200	160048	26736	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	43	80019	1	9	2	60	80040	6	1	59	43	19	1	1	1	5118	0	16	0	0	26734	13	13	5	80000	100	26737	26737	26737	26737	26786
80204	26739	200	1	0	0	0	0	70	1	3	26721	2	7	9	19	25	80100	100	80000	100	80013	500	1168224	0	49	23634	26714	26736	16664	6	16688	80116	200	80024	200	160048	26736	86	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	18	0	39	80039	6	1	40	43	0	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26793	26843	26728
80204	26727	200	0	0	0	0	0	45	1	0	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167542	0	49	23627	26736	26727	16660	6	16659	80115	200	80024	200	160048	26727	137	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	39	80039	0	1	39	43	0	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26829	26839	26729
80204	26707	200	0	0	0	0	0	45	1	1	26712	2	12	12	18	25	80100	100	80000	100	80015	500	1177116	1	49	23647	26727	26727	16635	6	16682	80114	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	6	1	39	43	0	1	1	1	5118	0	16	0	0	26704	10	10	4	80000	100	26708	26728	26796	26822	26731
80204	26707	200	0	0	0	0	0	45	1	1	26712	2	12	12	1	25	80100	100	80000	100	80015	500	1165856	1	49	23647	26727	26707	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	0	80039	6	1	39	43	0	1	1	1	5118	0	16	0	0	26724	10	0	4	80000	100	26728	26810	26728	26742	26784
80204	26737	200	0	0	0	0	0	45	1	1	26712	0	12	12	18	25	80100	100	80000	100	80015	500	1177116	1	49	23647	26727	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	3	80000	6	1	39	43	0	1	1	1	5118	0	16	0	0	26724	0	0	0	80000	100	26728	26728	26806	26839	26733
80204	26727	200	0	0	0	0	0	45	0	1	26692	2	0	12	18	25	80100	100	80000	100	80014	500	1167692	1	49	23627	26707	26707	16635	6	16682	80114	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	0	1	0	43	0	1	1	1	5118	0	16	0	0	26724	0	10	4	80000	100	26728	26728	26783	26845	26733
80204	26736	200	0	0	0	0	0	45	1	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1166596	1	49	23627	26707	26727	16655	6	16679	80114	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	0	0	39	80039	6	1	39	43	0	1	1	1	5118	0	16	0	0	26724	10	10	4	80000	100	26728	26728	26815	26829	26708
80204	26727	207	0	0	0	0	0	45	1	1	26712	2	12	12	18	25	80100	100	80000	100	80015	500	1177116	0	49	23647	26727	26727	16655	6	16679	80114	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	0	80039	6	1	39	43	0	1	1	1	5118	0	16	0	0	26704	10	10	4	80000	100	26728	26728	26763	26812	26731
80204	26727	200	0	0	0	0	0	45	0	0	26692	0	12	0	18	25	80100	100	80000	100	80015	500	1166596	1	49	23627	26727	26727	16655	6	16659	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80000	6	1	39	43	0	1	1	1	5118	0	16	0	0	26704	10	10	4	80000	100	26728	26728	26846	26813	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3343

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	0	0	0	0	0	0	0	45	1	0	1	26712	2	0	0	16	25	80010	10	80000	10	80000	50	1169222	1	49	23628	26727	26708	16672	3	16708	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	2448	80039	6	1	39	43	0	0	0	5020	0	17	16	9	17	26724	10	10	4	80000	10	26728	26728	26710	26728	26744
80024	26743	200	1	0	0	1	0	0	0	45	1	0	1	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1166896	1	49	23648	26727	26728	16672	3	16707	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	0	80039	0	1	0	42	80039	6	1	39	0	0	0	0	5021	1	13	17	16	14	26724	0	10	4	80000	10	26729	26729	26729	26729	26731
80024	26746	200	1	0	0	1	0	0	0	45	0	0	1	26712	2	12	12	0	25	80010	10	80000	10	80000	50	1167298	1	49	23656	26736	26736	16660	3	16695	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	20	43	80058	0	2	1	72	80040	6	1	19	43	19	0	0	5021	1	17	16	17	18	26733	13	13	5	80000	10	26737	26737	26737	26737	26745
80024	26744	200	1	1	0	1	1	0	0	66	1	0	3	26721	3	7	7	19	25	80010	10	80000	10	80000	50	1167791	1	49	23656	26715	26714	16681	3	16716	80010	20	80000	20	160000	26737	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	21	43	80060	0	1	1	27	80039	6	1	58	0	19	2	0	5021	1	16	16	17	16	26734	13	13	0	80000	10	26737	26737	26741	26737	26737
80024	26745	200	1	1	1	1	1	0	0	67	1	0	3	26699	2	0	0	19	25	80010	10	80000	10	80000	50	1169451	1	49	23635	26737	26736	16681	3	16716	80010	20	80000	20	160000	26715	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	21	43	80019	2	1	2	24	80040	6	1	59	43	19	2	0	5020	0	17	16	17	17	26733	13	13	5	80000	10	26737	26715	26737	26738	26744
80024	26741	200	1	1	1	1	0	0	0	67	1	0	3	26722	2	7	7	19	25	80010	10	80000	10	80000	50	1173975	1	49	23656	26736	26736	16681	3	16717	80010	20	80000	20	160000	26737	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	80058	1	1	0	64	80040	6	1	59	43	19	0	0	5021	1	17	16	14	17	26733	13	13	0	80000	10	26737	26716	26737	26737	26737
80024	26742	201	1	1	0	1	1	0	0	66	1	0	3	26721	0	7	7	19	25	80010	10	80000	10	80000	50	1167791	1	49	23656	26736	26737	16681	3	16716	80010	20	80000	20	160000	26736	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	80061	1	3	1	66	80040	6	1	58	43	19	1	0	5021	1	17	16	17	17	26734	13	13	5	80000	10	26715	26737	26737	26737	26819
80024	26749	200	1	1	1	1	1	0	0	66	0	0	3	26721	0	0	7	20	25	80010	10	80000	10	80000	50	1174408	1	49	23657	26736	26736	16660	3	16695	80010	20	80000	20	160000	26714	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	21	43	80059	1	0	0	30	80040	6	1	58	43	19	1	0	5021	1	17	16	10	17	26734	13	13	5	80000	10	26715	26715	26737	26737	26738
80024	26749	201	1	1	1	1	1	0	0	24	1	0	2	26721	3	7	7	19	25	80010	10	80000	10	80000	50	1167119	1	49	23657	26736	26715	16660	3	16716	80010	20	80000	20	160000	26717	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	19	43	80058	1	0	1	124	80040	6	1	57	43	19	1	0	5021	1	17	16	13	17	26717	13	13	5	80000	10	26737	26737	26737	26737	26737
80024	26744	201	1	1	1	1	1	0	0	67	1	0	2	26721	3	0	9	20	25	80010	10	80000	10	80000	50	1167219	1	49	23657	26736	26736	16682	3	16695	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80021	21	43	80060	0	0	2	67	80040	6	1	59	43	19	1	0	5021	1	17	16	14	17	26733	13	13	0	80000	10	26737	26737	26737	26737	26737

LDRSH (register, uxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations