Firestorm: SUBS (uxth, 32-bit) measurements

Code:

  subs w0, w0, w1, uxth

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	44	1	1	1001	1000	0	0	73	2	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	3	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	44	1	1	1001	1000	0	0	73	2	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, uxth

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20128	41	1	1	10201	100	99	100	10100	100	0	0	710	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	132	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	3	0	1080	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	5	1	10201	100	99	100	10100	100	1	0	710	2	39	2	2	19922	20050	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	6	0	170	10000	19862	25	20100	20100	10100	1305875	0	49	16955	20035	20083	18581	3	18746	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	1223	710	2	39	2	2	19922	20000	10100	20036	20036	20128	20130	20129
10204	20035	150	1	0	3	176	103	10000	19862	25	20100	20100	10100	1305121	1	49	17046	20035	20035	18581	7	18775	10335	10200	20200	20035	41	3	1	10201	100	99	100	10100	100	0	0	710	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	156	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	0	710	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	232	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	2	39	2	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	82	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	2	39	1	2	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18640	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	103	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	5	1	10021	10	9	10	10010	10	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, uxth

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	103	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	3	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	212	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20081	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	3	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	2	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	39	0	251	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	213	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20728	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	1	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, uxth
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	1	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1321	3	16	0	1	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1321	3	16	0	1	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	7	27486	20107	20224	30236	30079	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1321	3	16	3	3	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1321	1	16	1	3	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	0	0	3	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1322	3	16	0	1	29983	30015	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1321	3	16	3	1	29983	30000	20100	30036	30036	30082	30036	30036
20204	30035	225	1	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1322	1	16	3	1	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1319	3	16	3	1	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	1	1	1	1321	3	16	3	3	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	1	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	0	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1321	0	16	3	1	29982	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	4	33	3	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	2	33	2	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	3	33	3	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	1	1270	3	33	3	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	3	33	2	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	9	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	3	33	3	3	29959	30000	20010	30036	30036	30036	30036	30065
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	3	33	3	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	447	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	3	33	3	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	327	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	3	33	3	2	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	18	94	10000	29891	25	30010	30010	20086	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	1270	3	33	2	3	29959	30000	20010	30036	30036	30036	30036	30036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, uxth
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	251	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	4	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	29983	30000	20100	30036	30078	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	1013	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	0	75	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	351	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	363	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	2	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30082	30036	30036	30036	30082
20024	30035	225	1	0	45	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	318	156	10000	29891	25	30010	30010	20010	1957058	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	2	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	2	2005	2	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30080	224	0	1	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	1	3	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	414	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	12	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, uxth
  subs w1, w8, w9, uxth
  subs w2, w8, w9, uxth
  subs w3, w8, w9, uxth
  subs w4, w8, w9, uxth
  subs w5, w8, w9, uxth
  subs w6, w8, w9, uxth
  subs w7, w8, w9, uxth

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	0f	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	53414	400	1	0	0	61	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	144	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	84	5110	1	24	1	1	53432	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	161	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	186	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80205	53410	400	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	111	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	159	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	1	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	87	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	78	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	97	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	99	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	126	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	399	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	3	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	53401	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	11	24	10	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	10	24	10	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	9	24	10	10	53360	160000	80010	53381	53433	53381	53381	53381
80024	53380	400	0	0	0	0	61	80078	47951	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	10	24	10	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	6	24	6	10	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	82	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	10	24	6	10	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	10	24	10	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	9	24	10	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	1	49	47279	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	6	24	6	10	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	9	346	80000	47946	25	160010	160010	80010	3438130	0	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	0	10	80010	10	0	0	5020	10	24	10	6	53360	160000	80010	53381	53381	53381	53381	53381

SUBS (uxth, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations