Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (uxth, 32-bit)

Test 1: uops

Code:

  subs w0, w0, w1, uxth
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150611000186225200020001000126235020352035172931866100010002000203544111001100000732431119202000100020362036203620362036
10042035150611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203541111001100003731431119202000100020362036203620362036
10042035150611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035160611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203544111001100000732431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, uxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000006110000198622520100201001010013051210491695520035200351858131872010100102002020020128411110201100991001010010000710239221992220000101002003620036200362003620036
10204200351500001326110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
10204200351500030108010000198622520100201001010013051211491695520035200351858131872010100102002020020035415110201100991001010010010710239221992220050101002003620036200362003620036
1020420035150006017010000198622520100201001010013058750491695520035200831858131874610100102002020020035411110201100991001010010011223710239221992220000101002003620036201282013020129
102042003515010317610310000198622520100201001010013051211491704620035200351858171877510335102002020020035413110201100991001010010000710239221992220000101002003620036200362003620036
1020420035150000015610000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010010710239221992220000101002003620036200362003620036
1020420035150000023210000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000710239221992220000101002003620036200362003620036
102042003515000008210000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000710239121992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03091e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351864031874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035149000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
10024200351500001031000019862252001020010100101305229491695520035200351860331874010010100202002020035415110021109101001010000640241221993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, uxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351500000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000000710139111992220000101002003620036200362003620036
102042003515000000010310000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000000710139111992220000101002003620036200362003620036
10204200351500000006110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000000000710139111992220000101002003620036200362003620036
10204200351500000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000000710139111992220000101002003620036200362003620036
10204200351500000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000000710139111992220000101002003620036200362003620036
10204200351500000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000300710139111992220000101002003620036200362003620036
102042003515000000021210000198622520100201001010013051210491695520081200351858131872010100102002020020035411110201100991001010010000000000710139111992220000101002003620036200362003620036
10204200351500000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000300710139111992220000101002003620036200362003620036
10204200351500000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000000710139211992220000101002003620036200362003620036
1020420035150000039025110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
1002420035150021361100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020207282003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101001640241221993020000100102003620036200362003620036
10024200351500061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000640241221993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, uxth
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522510006110000298992530100301002010719562404926955030035300352739172748620107202243023630035851120201100991002010010100000001111321316012998330000201003003630036300363003630036
202043003522510006110000298992530100301002010719562404926955030035300352739172748620107202243023630035851120201100991002010010100000001111321316012998330000201003003630036300363003630036
202043003522510006110000298992530100301002010719562404926955030035300352739172748620107202243023630079851120201100991002010010100000001111321316332998230000201003003630036300363003630036
202043003522500006110000298992530100301002010719562404926955030035300352739172748520107202243023630035851120201100991002010010100000001111321116132998330000201003003630036300363003630036
202043003522510036110000298992530100301002010719562404926955030035300352739182748620107202243023630035851120201100991002010010100000001111322316012998330015201003003630036300363003630036
202043003522500006110000298992530100301002010719562404926955030035300352739182748520107202243023630035851120201100991002010010100000001111321316312998330000201003003630036300823003630036
202043003522510006110000298992530100301002010719562404926955030035300352739182748520107202243023630035851120201100991002010010100000001111322116312998230000201003003630036300363003630036
202043003522500006110000298992530100301002010719562404926955030035300352739172748620107202243023630035851120201100991002010010100000001111319316312998230000201003003630036300363003630036
202043003522500006110000298992530100301002010719562404926955030035300352739172748620107202243023630035851120201100991002010010100000031111321316332998230000201003003630036300363003630036
202043003522510006110000298992530100301002010719562404926955030035300352739182748620107202243023630035851120201100991002010010100000001111321016312998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001001270433332995930000200103003630036300363003630036
20024300352250611000029891253001030010200101956289149269553003530035273913274982001020020300203003585112002110910200101001001270233232995930000200103003630036300363003630036
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001001270333332995930000200103003630036300363003630036
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001011270333332995930000200103003630036300363003630036
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001001270333232995930000200103003630036300363003630036
20024300352259611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001001270333332995930000200103003630036300363003630065
20024300352250611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001001270333332995930000200103003630036300363003630036
2002430035225447611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001001270333332995930000200103003630036300363003630036
2002430035225327611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001001270333322995930000200103003630036300363003630036
200243003522518941000029891253001030010200861956289049269553003530035273913274982001020020300203003585112002110910200101001001270333232995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, uxth
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225025110000298992530100301002010719562404926955300353003527391727486201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562404926955300353003527391727485201072022430236300358511202011009910020100101000001111320162998330000201003003630036300363003630036
202043003522406110000298992530100301002010719562404926955300353003527391827486201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562404926955300353003527391827485201072022430236300358511202011009910020100101000041111319162998230000201003003630036300363003630036
202043003522506110000298992530100301002010719562404926955300353003527391727486201072022430236300358511202011009910020100101000001111320162998330000201003003630078300363003630036
202043003522506110000298992530100301002010719562404926955300353003527391727485201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036
202043003522506110000298992530100301002010719562404926955300353003527391727485201072022430236300358511202011009910020100101000001111319162998230000201003003630036300363003630036
202043003522506110000298992530100301002010719562404926955300353003527391827485201072022430236300358511202011009910020100101000001111319162998230000201003003630036300363003630036
202043003522506110000298992530100301002010719562404926955300353003527391727486201072022430236300358511202011009910020100101000001111320162998230000201003003630036300363003630036
20204300352250101310000298992530100301002010719562404926955300353003527391827486201072022430236300358511202011009910020100101000001111319162998330000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225007561100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
20024300352250035161100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
20024300352240036361100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100200001270133112995930000200103008230036300363003630082
2002430035225104561100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
200243003522400318156100002989125300103001020010195705804926955300353003527391327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
200243003522500061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100000001270233112995930000200103003630036300363003630036
200243003522500061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100022005201270133112995930000200103003630036300363003630036
200243008022401061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100013001270133112995930000200103003630036300363003630036
20024300352250041461100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100000001270133112995930000200103003630036300363003630036
2002430035225000611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000012001270133112995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, uxth
  subs w1, w8, w9, uxth
  subs w2, w8, w9, uxth
  subs w3, w8, w9, uxth
  subs w4, w8, w9, uxth
  subs w5, w8, w9, uxth
  subs w6, w8, w9, uxth
  subs w7, w8, w9, uxth
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03l1i tlb fill (04)0f1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045341440010061800004874125160100160100801003440005049503305341053410432982909343360801008020016020053410391180201100991008010010000014451101241153390160000801005341153411534115341153411
80204534104000006180000487412516010016010080100344000514950330534105341043298302434336080100802001602005341039118020110099100801001000008451101241153432160000801005341153411534115341153411
8020453410400000161800004874125160100160100801003440005149503305341053410432982909343360801008020016020053410391180201100991008010010000018651101241153390160000801005341153411534115341153411
802055341040000061800004874125160100160100801003440005049503305341053410432983024343360801008020016020053410391180201100991008010010000011151101241153390160000801005341153411534115341153411
802045341040000061800004874125160100160100801003440005149503305341053410432983024343360801008020016020053410391180201100991008010010000015951101241153390160000801005341153411534115341153411
80204534104000106180000487412516010016010080100344000514950330534105341043298290934336080100802001602005341039118020110099100801001000008751101241153390160000801005341153411534115341153411
80204534104000006180000487412516010016010080100344000514950330534105341043298302434336080100802001602005341039118020110099100801001000007851101241153390160000801005341153411534115341153411
80204534104000009780000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001000009951101241153390160000801005341153411534115341153411
802045341040000061800004874125160100160100801003440005049503305341053410432982909343360801008020016020053410391180201100991008010010000012651101241153390160000801005341153411534115341153411
8020453410399000618000048741251601001601008010034400050495033053410534104329830243433608010080200160200534103911802011009910080100100000351101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)0309l2 tlb miss data (0b)181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800245340140000006180000479462516001016001080010343813001495030053380533804329032513433528001080020160020533803911800211090108001010005020112410653360160000800105338153381533815338153381
800245338040000006180000479462516001016001080010343813001495030053380533804329027493433528001080020160020533803911800211090108001010005020102410653360160000800105338153381533815338153381
800245338040000006180000479462516001016001080010343813001495030053380533804329032513433528001080020160020533803911800211090108001010005020924101053360160000800105338153433533815338153381
800245338040000006180078479512516001016001080010343813001495030053380533804329029363433528001080020160020533803911800211090108001010005020102410653360160000800105338153381533815338153381
80024533804000000618000047946251600101600108001034381300149503005338053380432902936343352800108002016002053380391180021109010800101000502062461053360160000800105338153381533815338153381
800245338040000008280000479462516001016001080010343813001495030053380533804329029363433528001080020160020533803911800211090108001010005020102461053360160000800105338153381533815338153381
800245338039900006180000479462516001016001080010343813001495030053380533804329032513433528001080020160020533803911800211090108001010005020102410653360160000800105338153381533815338153381
80024533804000000618000047946251600101600108001034381300149503005338053380432902936343352800108002016002053380391180021109010800101000502092410653360160000800105338153381533815338153381
80024533803990000618000047946251600101600108001034381300149472795338053380432903251343352800108002016002053380391180021109010800101000502062461053360160000800105338153381533815338153381
8002453380400000934680000479462516001016001080010343813001495030053380533804329032513433528001080020160020533803911800211090108001010005020102410653360160000800105338153381533815338153381