Firestorm: ADD (sxtw, 32-bit) measurements

Code:

  add w0, w0, w1, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	9	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	3	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	0	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	0	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	0	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	0	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	0	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	0	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	0	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	27	73	2	41	2	2	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  add w0, w0, w1, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	0	84	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	1	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	82	9877	25	10100	10100	10100	88664	49	7001	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	164	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	176	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	251	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	164	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	227	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	82	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	281	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	4	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	1	3	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10080	41	2	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	6	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	189	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	45	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10082	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10189	20020	10035	41	1	1	10021	10	9	10	10010	10	0	2	1	1215	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	93	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	3	41	3	3	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  add w0, w1, w0, sxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	237	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	2438	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	3	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	273	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	252	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	9	61	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	15	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	880	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	164	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	531	9863	25	10010	10010	10010	88784	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 4: throughput

Count: 8

Code:

  add w0, w8, w9, sxtw
  add w1, w8, w9, sxtw
  add w2, w8, w9, sxtw
  add w3, w8, w9, sxtw
  add w4, w8, w9, sxtw
  add w5, w8, w9, sxtw
  add w6, w8, w9, sxtw
  add w7, w8, w9, sxtw

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13419	100	1	0	0	163	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	3	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	40	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	0	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	1	0	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	0	0	100	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	1	0	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	35	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	403	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	3	5110	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	0	0	473	25	80100	80100	80100	400500	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	13377	100	0	392	25	80010	80010	80010	400050	0	0	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	4	0	0	3	5021	0	0	6	19	3	2	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	0	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5021	0	0	6	19	5	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	0	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	1	0	0	5021	0	0	3	19	5	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	1	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	3	5021	0	0	6	19	2	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	390	25	80010	80010	80010	400050	0	1	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	1	0	0	5021	0	0	3	19	5	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	425	25	80010	80010	80010	400050	0	0	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5021	0	0	2	19	2	4	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	451	25	80010	80010	80010	400050	0	1	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5021	0	0	5	19	3	2	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	0	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5022	0	0	3	19	3	2	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	0	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5021	0	0	2	19	2	3	17319	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	35	25	80010	80010	80010	400050	0	1	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5021	0	0	6	19	8	7	13368	80000	80010	13372	13372	13372	13372	13372

ADD (sxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations