Firestorm: CMN (register, lsr, 64-bit) measurements

Code:

  cmn x0, x1, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6b	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	709	5	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	25	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	5	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	21	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	6	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	25	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	5	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	21	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	5	1	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	21	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	5	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	25	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	6	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	21	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	5	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	21	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	5	0	82	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	21	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710
1004	709	5	0	61	1000	304	25	2000	2000	1000	40877	0	0	709	709	498	25	3	561	1000	1000	2000	709	78	1	1	1001	1000	0	0	73	2	22	2	2	684	2000	710	710	710	710	710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, x1, lsr #17
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	224	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	159	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	6	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	3	1	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	1	0	1	3	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	3	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	6	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	147	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	6	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	6	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	2	66	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	14	33	8	13	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	2	66	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	15	33	12	13	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	2	66	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	14	33	13	14	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	3	2	731	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	14	33	12	14	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	2	66	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	14	33	14	13	29958	30000	10010	30036	30036	30036	30036	30065
20024	30035	225	0	2	66	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	14	33	13	12	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	2	351	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	13	33	14	13	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	2	731	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20022	10	9	10	20010	10010	0	0	0	0	1274	13	33	12	14	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	2	66	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	13	33	6	13	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	2	66	10000	29891	25	30010	30010	20010	1956289	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	0	1274	13	33	14	13	29958	30000	10010	30036	30036	30036	30036	30036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, x1, lsr #17
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	0	0	1	537	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20199	20200	30334	30081	145	2	1	20201	100	99	100	20100	10100	7	4	0	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	1	49	26955	30035	30035	27400	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	1	6	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	726	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	2	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	61	10000	29893	25	30100	30100	20100	1956198	0	49	26955	30035	30035	27369	3	27478	20100	20200	30200	30035	145	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	1310	1	2	31	2	2	29954	30000	10100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	1	3	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	499	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	2	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	156	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	726	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	726	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	225	0	251	10000	29891	25	30010	30010	20010	1956289	0	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036
20024	30035	224	0	61	10000	29891	25	30010	30010	20010	1956289	1	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	145	1	1	20021	10	9	10	20010	10010	0	0	0	1270	0	1	33	1	1	29958	30000	10010	30036	30036	30036	30036	30036

Test 4: throughput

Count: 8

Code:

  cmn x0, x1, lsr #17
  cmn x0, x1, lsr #17
  cmn x0, x1, lsr #17
  cmn x0, x1, lsr #17
  cmn x0, x1, lsr #17
  cmn x0, x1, lsr #17
  cmn x0, x1, lsr #17
  cmn x0, x1, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	53412	400	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2060	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	24	3	4	53392	160000	100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	168	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2050	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	24	4	4	53392	160000	100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	124	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2050	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	3	24	4	4	53392	160000	100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	271	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2060	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	24	4	4	53392	160000	100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	233	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2063	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	6	0	5110	4	24	3	4	53392	160000	100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	321	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2060	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	24	4	5	53392	160000	100	53468	53627	53411	53411	53522
80204	53469	400	0	0	0	0	9	0	0	624	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2063	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	0	5110	3	24	4	3	53392	160000	100	53411	53411	53411	53411	53524
80204	53410	400	0	0	0	0	9	0	0	383	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2060	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	5110	4	24	4	3	53392	160000	100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	33	0	0	61	80000	48741	37	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2060	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	24	3	4	53392	160000	100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	0	49	50330	53410	53410	43298	2050	3	43360	80100	80200	160200	53410	78	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	4	24	5	4	53392	160000	100	53411	53411	53411	53411	53411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	53401	400	0	0	0	0	0	192	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2562	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	0	3	24	0	3	2	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	0	27	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2707	3	43372	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	0	2	24	0	3	3	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	0	42	0	61	80000	47946	25	160010	160010	80010	3438130	1	0	49	50300	53380	53380	43290	2562	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	5	0	3	24	1	2	3	53359	160000	16	10	53381	53381	53381	53381	53381
80024	53380	400	1	0	0	0	0	27	0	816	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2707	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	7	0	0	0	0	5020	0	0	3	24	0	2	3	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	27	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2562	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	0	3	24	0	3	2	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	27	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2707	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	0	3	24	0	3	3	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	48	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2562	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	0	3	24	0	2	3	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	0	27	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2707	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	1	0	5020	0	0	2	24	0	3	3	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53432	400	0	0	0	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2562	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	0	2	24	0	2	3	53359	160000	0	10	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	0	0	39	0	61	80000	47946	25	160010	160010	80010	3438130	0	0	49	50300	53380	53380	43290	2707	3	43352	80010	80020	160020	53380	78	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	0	3	24	3	3	2	53359	160000	0	10	53381	53381	53381	53381	53381

CMN (register, lsr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations