Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CRC32H

Test 1: uops

Code:

  crc32h w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100430332300711922251000100010008144040303330332760328911000100020003033380111001100000731161129391000100030343034303430343034
100430332200611922251000100010008144040303330332760328911000100020003033380111001100000731161129391000100030343034303430343034
100430332300611922251000100010008144040303330332760328911000100020003033380111001100000731161129391000100030343034303430343034
100430332300611922251000100010008144040303330332760328911000100020003033380111001100003731161129391000100030343034303430343034
100430332300611922251000100010008144040303330332760328911000100020003033380111001100000731161129391000100030343034303430343034
1004303323012611922251000100010008144040303330332760328911000100020003033380111001100000731161129391000100030343034303430343034
100430332200611922251000100010008144040303330332760328911000100020003033380111001100010731161129391000100030343034303430343034
100430332200611922251000100010008144040303330332760328911000100020003033380111001100000731161129391000100030343034303430343034
100430332200611922251000100010008144040303330332760328911000100020003033380111001100003731161129391000100030343034303430343034
100430332300611922251000100010008144040303330332760328911000100020003033380111001100000731161129391000100030343034303430343034

Test 2: Latency 1->2

Code:

  crc32h w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102043003322506119922251010010100101008289401492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101008289401492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101468289401492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
1020430033225018919922251010010100101008289401492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
102043003322406119922251010010100101008289400492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
102043003322406119922251010010100101008289401492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
1020430033225019319922251010010100101008289400492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003020830034300783003430034
102043003322506119922251010010100101008289400492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
102043003322506119922251010010108101008289401492695303003330033286103287411010010200202003003337411102011009910010100100000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101008289400492695303003330033286103287411010010200202003003337411102011009910010100100030710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4d5051schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332330000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640316222993910000100103003430034300343003430034
10024300332250000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250000061199220251001010010100108284901492695330033300332863232876310010100202002030208380111002110910100101000640216222993910008100103003430034300343003430034
10024300332250000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101010640216222993910000100103003430034300343003430034
10024300332240000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332250000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332240000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
10024300332240000061199220251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034

Test 3: Latency 1->3

Code:

  crc32h w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020430033225000000029819922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
102043003322500000006119922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
102043003322500000006119922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
102043003322500000006119922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
1020430033225000000022919922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
102043003322500000006119922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
102043003322400000006119922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
1020430033233000000020819922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
102043003322500000006119922251010010100101008289401492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034
102043003322400000006119922251010010100101008290381492695330033300332861032874110100102002020030033374111020110099100101001000000000710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)1e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250000191119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101003640316222993910000100103003430034300343003430034
1002430033225000061199222510010100101001082849004926953300333003328632112876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322500006119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322500006119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101003640216222993910000100103003430034300343020730034
1002430033225000010319922251001010010100108284900492695330033300332863232876310010100202002030076380111002110910100101000640216222993910007100103003430034300343003430034
100243003322500006119922251001010010100108284901492695330033300762863272879110010100202011830033380111002110910100101001006640224242993910000100103003430034300343003430077
1002430033225100010319922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101003640216222993910000100103003430034300343003430034
100243003322500006119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034300343003430034
100243003322500006119922251001010010100108284900492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103007730034300343003430034
100243007722500006119922251001010010100108284901492695330033300332863232876310010100202002030033380111002110910100101000640216222993910000100103003430034302073003430034

Test 4: throughput

Count: 8

Code:

  crc32h w0, w8, w9
  crc32h w1, w8, w9
  crc32h w2, w8, w9
  crc32h w3, w8, w9
  crc32h w4, w8, w9
  crc32h w5, w8, w9
  crc32h w6, w8, w9
  crc32h w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204800355990000046258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100000000005110216118003180000801008003680036800368003680036
80204800356000000046258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100220000005110116118003180000801008003680036802178003680082
80204800356000000046258010080100801004005001497392380035800356996436999380100802001602008003516411802011009910080100100000000005110116118003180000801008015480036800368003680036
80204800355990000088258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100002000005110116118003180000801008003680036800368003680036
80204800356000000046258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100000010645110116118003180000801008003680036800368003680036
80204800355990000046258010080190801004005001497695580035800356996436999380100802001604648003516411802011009910080100100000000005110216118003180000801008003680036800368003680036
80204802145990004046258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100000000005110116118003180000801008003680036800368003680036
80204800355990000046258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100000000005110116118003180000801008021880036800368003680036
80204800356000000046258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100000010005110116118003180000801008003680036800368003680217
802048003560000000172258010080100801004005001497695580035800356996436999380100802001602008003516411802011009910080100100000000005160116118003180000801008021780036800368003680036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? int retires (ef)f5f6f7f8fd
80024800356000000462580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000300150202162280032800000800108003680036800368003680036
80024800356000000462580010800108001040005014976955800358003569986370015800108002016002080035164118002110910800101000000050202162280032800000800108003680036800368003680036
80024800355990000462580010800108003340005004976955800358003569986370015800108002016002080035164118002110910800101000000050202162280032800000800108003680036800368003680036
800248003559900005212580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000000050202162280032800000800108003680075800368003680036
80024800355990000462580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000030050202162380032800000800108003680036800368003680036
80024800355990000462580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101003000050202162280032800000800108003680036800368003680036
8002480035599001207112580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000000050202162280032800000800108003680036800368003680036
800248003559900006162580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000000050202162280032800000800108003680036800368003680036
8002480035599001202362580010800108001040005004976955800358003569986370015800108002016002080035164118002110910800101000000050202162280032800000800108003680036800368003680036
80024800355990000462580010800108001040005004976955800808003569986370015800108006416002080035164118002110910800101000000050202162280032800000800108003680036800368003680036