Firestorm: TBNZ (not taken) measurements

Code:

  tbnz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3898	6	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	2	21	1	1	532	536	536	536	536	536
1004	535	3	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	51	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	3	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	3	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536

Count: 8

Code:

  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	40518	301	0	0	49	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	1	16	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091
80204	40090	301	0	0	28	28	80110	80110	80114	400560	1	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40570	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091
80204	40090	301	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40421
80204	40090	300	0	0	123	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091
80204	40090	301	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	0	0	0	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091
80204	40090	300	0	0	28	28	80110	80110	80114	400560	0	49	37010	40090	40090	13349	7	13359	80114	80224	80224	40090	32050	1	1	80201	80100	99	100	100	100	7	0	2	0	1	1	1	5118	0	16	40087	100	40091	40091	40091	40091	40091

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80024	42573	308	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	9	20	3	6	10	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	10	20	0	9	7	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	5	20	0	7	9	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	6	20	0	7	5	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	8	20	0	5	8	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	5	20	0	5	7	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	11	20	0	6	8	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	0	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	0	11	20	2	7	6	40037	10	40041	40041	40041	40041	40041
80024	40040	300	9	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	5	1	6	179	0	9	6	40037	10	40041	40041	40041	40041	40041
80024	40040	300	0	35	25	80010	80010	80010	400050	1	0	49	36960	40040	40040	13331	3	13349	80010	80020	80020	40040	40040	1	1	80021	80010	9	10	10	10	0	0	0	0	0	0	5020	0	5	10	20	0	4	7	40037	10	40041	40041	40041	40041	40041

TBNZ (not taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations