Firestorm: CMP (sxtx, 64-bit) measurements

Code:

  cmp x0, x1, sxtx

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	369	2	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	18	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	15	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	0	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	1	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	0	73	1	18	1	1	366	1000	370	370	370	370	370

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp x0, x1, sxtx
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	103	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20454	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	3	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	1	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	84	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	45	3	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	166	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	128	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	20013	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	126	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	494	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	68	3	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	45	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	2	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	363	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	2	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	82	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	149	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp x0, x1, sxtx
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	126	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	49	3	0	1310	1	3	28	3	3	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20360	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	3	20010	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	300	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	3	28	3	3	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	4229	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	3	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	3	28	2	3	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	2	1310	1	2	28	3	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	99	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	602	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	1310	1	2	28	2	3	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	4	27	4	4	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	387	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	4	27	4	3	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	4	27	4	4	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	408	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1270	4	27	4	4	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	1335	6	67	8	7	20130	20091	10010	20217	20256	20219	20261	20263
20024	20262	152	1	0	0	0	0	5	5	528	440	0	1788	19914	110	20123	20100	20092	1300372	0	49	17182	20260	20260	17484	21	17605	20421	20394	30738	20035	104	5	1	20021	10	9	10	20010	10010	2	2	0	1	0	4055	2	1343	7	66	7	5	20191	20022	10010	20251	20263	20127	20218	20218
20024	20261	152	0	1	0	1	0	6	5	660	440	0	1195	19917	127	20121	20123	20341	1300384	0	49	17181	20264	20262	17477	25	17634	20423	20491	30737	20260	104	6	1	20021	10	9	10	20010	10010	0	0	0	0	0	4053	4	1303	8	69	6	6	20162	20111	10010	20262	20263	20264	20261	20264
20024	20262	152	0	1	1	0	1	6	5	660	440	0	1321	19915	126	20121	20122	20423	1300445	0	49	16999	20262	20262	17484	25	17657	20010	20490	30733	20261	104	6	1	20021	10	9	10	20010	10010	0	4	0	0	0	4680	0	1339	6	68	7	6	20137	20111	10010	20262	20036	20309	20259	20218
20024	20300	152	0	1	0	1	1	5	6	1050	440	0	2029	19912	124	20143	20122	20422	1300384	0	49	17181	20217	20260	17474	16	17657	20505	20576	31006	20306	104	8	1	20021	10	9	10	20010	10010	0	2	2	0	4	4898	2	1354	10	68	6	7	20061	20089	10010	20261	20080	20263	20263	20261
20024	20261	150	0	1	0	2	1	2	5	132	440	1	852	19917	109	20078	20126	20423	1299756	0	49	17000	20081	20262	17446	27	17528	20423	20117	30300	20172	104	6	1	20021	10	9	10	20010	10010	4	0	2	1	0	4060	4	1270	4	27	3	4	19995	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  cmp x0, x1, sxtx
  cmp x0, x1, sxtx
  cmp x0, x1, sxtx
  cmp x0, x1, sxtx
  cmp x0, x1, sxtx
  cmp x0, x1, sxtx
  cmp x0, x1, sxtx
  cmp x0, x1, sxtx

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26739	201	180	943	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	3	0	5110	2	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	201	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	1	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	146	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	6	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	201	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80183	80200	160200	26798	66	2	1	80201	100	99	100	80100	100	0	1	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	98	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	1	5110	1	19	2	3	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	98	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	100	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80205	26735	200	0	560	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	201	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	2	0	0	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26777	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	19	2	1	26731	80000	100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26720	200	0	3	0	35	25	80010	80010	80010	400050	1	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	5	18	4	4	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	1	49	23625	3	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	4	18	3	4	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	3	18	4	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	199	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	3	18	4	4	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	199	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	4	18	4	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	636	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	4	18	3	4	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	12	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	3	18	4	4	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	4	18	4	3	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	4	18	4	4	26701	80000	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	149	25	80010	80010	80010	400050	1	49	23625	0	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	5020	4	18	3	4	26701	80000	10	26706	26706	26706	26706	26706

CMP (sxtx, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations