Firestorm: PACDB measurements

Code:

  pacdb x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	67	0	0	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	16	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	0	0	0	0	0	126	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	2	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	68	0	0	0	0	0	0	0	0	103	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	24	0	3	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	68	0	0	0	0	0	0	0	0	103	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	3	0	75	2	85	2	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	68	0	0	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	2	0	0	0	73	1	85	1	2	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	74	0	0	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	6	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	68	0	0	0	0	0	0	0	0	104	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	0	0	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	1	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  pacdb x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	617	0	0	441	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68491	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	103	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	651	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	232	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	1	3	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	726	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	732	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	99	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70108	70030	70030	70030	70070
10204	70029	622	1	0	124	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10104	0	10100	70030	70030	70030	70030	70030
10204	70029	623	0	6	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	50	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	626	0	0	0	0	81	0	411	59824	0	25	10020	10020	10020	1807430	1	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	640	0	2	79	3	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	103	59824	0	25	10020	10020	10020	1807430	1	5	49	66949	0	70029	70187	68502	3	68696	10020	10020	20020	70029	1740	1	1	10021	10	9	10010	0	0	0	0	0	0	0	640	5	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	71	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	768	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	61	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	3	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	89	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	61	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70184	68514	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	3	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	61	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	61	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	12	0	61	59824	0	25	10020	10020	10020	1807430	0	0	49	66949	0	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  pacdb x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	697	0	0	0	0	114	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	75	0	1910	2	72	1	1	79809	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	750	0	0	0	0	0	0	156	69799	25	20200	20200	20200	4943304	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	12	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80076	80030
30204	80029	709	0	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75952	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	1	192	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	9	0	726	69799	109	20200	20200	20200	4942634	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80075	144	1	1	30201	100	99	30100	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	9	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	12	0	726	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	0	61	69799	25	20204	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40360	80029	144	1	1	30201	100	99	30100	0	0	102	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	1	0	0	0	103	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	1910	1	72	1	1	79794	20100	0	30100	80030	80075	80030	80030	80030
30204	80029	697	0	0	0	0	12	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	9	0	1910	1	72	1	1	79794	20100	0	30100	80030	80030	80030	80030	80030
30204	80029	695	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	1	49	77370	80029	80074	75961	3	76181	20200	20200	40362	80029	144	1	1	30201	100	99	30100	0	1	82983	4	2635	1	392	1	1	80820	20190	0	30100	80030	80030	80030	80030	80030

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
30024	80029	695	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80079	144	1	1	30021	10	9	30010	0	0	0	0	0	219	0	1890	5	72	4	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	743	0	0	0	0	0	0	12	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	3	0	0	0	1890	3	72	4	4	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	0	0	103	69799	25	20020	20020	20020	4952048	1	49	76949	80060	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	1890	4	72	4	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	98	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	10	0	0	0	1890	3	72	3	4	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	699	0	0	0	0	0	0	0	0	0	1298	69799	25	20020	20038	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20088	20020	40020	80029	144	2	1	30021	10	9	30010	0	0	0	7	0	0	0	1890	4	72	4	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	742	0	0	0	0	0	0	0	0	0	768	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	1890	3	72	3	4	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	698	0	0	0	0	0	0	12	0	0	103	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	1890	4	72	4	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	698	0	0	0	0	0	0	12	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76994	80074	80120	75983	3	76208	20082	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	28	0	3	0	1890	4	72	4	4	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	704	0	0	0	0	0	0	12	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80060	144	1	1	30021	10	9	30010	0	0	0	4	0	3	0	1890	4	72	4	3	79803	20010	0	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	0	0	61	69799	25	20020	20040	20020	4952048	1	49	76949	80029	80029	75983	3	76208	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	5	0	0	0	1890	4	72	4	3	79803	20010	0	30010	80030	80030	80030	80030	80030

Test 4: throughput

Count: 8

Code:

  pacdb x0, x8
  pacdb x1, x8
  pacdb x2, x8
  pacdb x3, x8
  pacdb x4, x8
  pacdb x5, x8
  pacdb x6, x8
  pacdb x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80204	80085	791	0	0	0	0	0	0	12	0	28	29	80205	80205	80207	401030	1	49	76960	80040	80041	69980	7	69990	80207	80224	160248	80041	164	1	1	80201	100	99	80100	0	0	0	5	0	0	0	1	1	1	5119	1	16	1	1	80037	80105	0	80100	80041	80041	80042	80042	80222
80204	80040	744	0	0	0	0	0	0	0	0	33	29	80205	80205	80207	401030	1	49	76961	80040	80041	69980	7	69990	80207	80224	160248	80040	164	1	1	80201	100	99	80100	0	0	0	2	0	0	0	1	1	1	5119	1	16	1	1	80038	80105	0	80100	80081	80041	80041	80041	80042
80204	80040	699	0	0	0	0	0	0	0	0	28	28	80205	80205	80207	401030	1	49	76960	80041	80040	69980	8	69990	80207	80224	160248	80040	164	1	1	80201	100	99	80100	0	0	0	82	0	0	0	1	1	1	5119	1	16	1	1	80038	80105	0	80100	80041	80042	80042	80042	80042
80204	80041	703	0	0	0	0	0	0	0	0	2772	174	80352	80373	80340	401896	1	49	77322	80358	80447	70121	44	70288	80317	80224	160248	80040	164	1	1	80201	100	99	80100	0	0	0	7	0	0	0	1	1	1	5120	1	16	1	1	80038	80105	0	80100	80042	80042	80041	80041	80041
80204	80040	697	0	0	0	0	0	0	0	1	312	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80025	80100	2	80100	80036	80036	80036	80036	80036
80204	80035	746	0	0	0	0	0	0	0	0	700	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	3	0	0	0	0	0	0	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	4	2	0	0	0	0	0	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	697	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	2	0	0	0	0	0	0	5110	3	25	4	4	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	1	0	0	0	0	0	0	0	63	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	15	0	0	0	0	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	2	0	3	0	0	0	0	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	80052	694	0	0	0	0	12	0	35	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	70018	3	70006	80020	80020	160020	80035	164	2	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	0	5020	0	4	25	0	3	3	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	748	0	0	0	0	0	0	77	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	70002	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	34	0	0	0	0	0	5020	0	3	25	0	3	3	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80083	164	1	1	80021	10	9	80010	0	0	0	0	0	2	0	0	0	0	0	5020	0	3	25	0	3	2	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	63	25	80020	80020	80020	400100	0	98	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	52	0	0	0	0	0	5020	0	2	25	0	2	3	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	5	0	500	0	0	0	5020	0	3	25	0	3	2	80024	80010	0	0	80010	80036	80036	80036	80081	80081
80024	80035	749	0	0	0	0	12	0	77	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	2	34	0	3	0	0	0	5020	0	4	25	0	2	3	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	752	0	0	0	0	0	0	77	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	74	0	3	0	0	1	5020	0	2	25	0	2	3	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	749	0	0	0	0	0	0	77	25	80104	80020	80020	400100	0	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	0	5020	0	2	25	0	2	3	80024	80010	0	0	80010	80036	80036	80036	80036	80070
80024	80035	700	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	1	0	0	0	0	0	5020	0	2	25	0	2	3	80024	80010	0	0	80010	80036	80036	80036	80036	80036
80024	80035	749	0	0	0	1	0	0	77	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	6	0	3	0	0	0	5020	0	3	25	0	3	2	80024	80010	0	0	80010	80036	80036	80036	80036	80036

PACDB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations