Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMN (register, asr, 64-bit)

Test 1: uops

Code:

  cmn x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100470950611000304252000200010004087717097094982135611000100020007097811100110000073322116842000710710710710710
100470950611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
1004709501051000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087707097094982535611000100020007097811100110000073122116842000710710710710710
100470950841000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073122116842000710710710710710
100470960611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087707097094982135611000100020007097811100110000073122116842000710710710710710
100470950611000304252000200010004087717097094982535611000100020007097811100110000073122116842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, x1, asr #17
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035224061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231232995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101331222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619814926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225094100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101331222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522500007261000029891253001030010200101956289149269553003530035273913274982001220020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352251000611000029891253001030010200101956287049269553003530035273913274982001020020300203003514511200211091020010100100701270133112995830000100103003630036300363003630036
200243003522500002511000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233112995830000100103003630036300363003630036
200243003522500007261000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
200243003522400003461000029891253001230010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
200243003522500007261000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352250000611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352251000611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352250000661000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036
20024300352250000631000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270133112995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, x1, asr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522500003971000029906253012730152201001956905049269553003530035273693274782010020200302003003514511202011009910020100101000000013100231222995430000101003003630036300363003630036
20204300352250000611000029893253010030100201001956198149269553003530035273693274782010020200302003003514511202011009910020100101000000013101231222995430000101003003630036300363003630036
20204300352240000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000013821231222995430000101003003630036300363003630036
20204300352250000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000100013101231222995430000101003003630036300363003630036
20204300352250000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000013101231222995430000101003003630036300363003630036
202043003522500150611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000030013101231232995430000101003008230036300363003630127
20204300352251000611000629893253010030132201001956929149269553003530035273693274782010020200302003003514511202011009910020100101000000013101231222995430000101003003630036300363003630036
20204300352250000611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000030013101231222995430000101003003630036300363003630036
2020430035225000108611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000013101231222995430000101003003630219300363003630036
202043003522500210611000029893253010030100201001956198049269553003530035273693274782010020200302003003514511202011009910020100101000000013101231223001830000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270233122995830000100103003630036300363003630036
2002430035224006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270333342995830000100103003630036300363003630036
2002430035225006110000298912530010300342001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270333342995830000100103003630036300363003630036
2002430035225006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270433232995830000100103003630036300363003630036
2002430035225006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270233222995830000100103003630036300363003630036
2002430035225006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270233222995830000100103003630036300363003630036
2002430035224006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270233222995830000100103003630036300363003630036
2002430035224006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270433112995830000100103003630036300363003630036
2002430035225006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270233222995830000100103003630036300673003630036
2002430035225006110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100101270233222995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmn x0, x1, asr #17
  cmn x0, x1, asr #17
  cmn x0, x1, asr #17
  cmn x0, x1, asr #17
  cmn x0, x1, asr #17
  cmn x0, x1, asr #17
  cmn x0, x1, asr #17
  cmn x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204534564000618000048741251601001601008010034400051349503305341053410432982063343360801008020016020053410781180201100991008010010000005110022411533921601081005341153411534115341153411
80204534104000668000048741251601001601008010034400051349503305341053410432982063343360801008020016020053410781180201100991008010010000005110312411533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400051349503305341053410432982060343360801008020016020053410781180201100991008010010000005110312411533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400051349503305341053410432982060343360801008020016020053410781180201100991008010010000005110312411533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400051349503305341053410432982063343360801008020016020053410781180201100991008010010000005110312411533921600001005341153411534115341153411
802045341040007268000048741251601001601008010034400051349503305341053410432982063343360801008020016020053410781180201100991008010010000005110312411533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400051349503305341053410432982050343360801008020016020053410781180201100991008010010000005110012411533921600001005341153411534115341153411
80204534104000848000048741251601001601008010034400050049503305341053410432982050343360801008020016020053410781180201100991008010010000005110012411533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400050049503305341053410432982063343360801008020016020053410781180201100991008010010000005110012411533921600001005341153411534115341153411
80204534104000618000048741251601001601008010034400050049503305341053410432982060343360801008020016020053410781180201100991008010010000005110012411533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)033f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024534024006180000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000050203244453359160000105338153381533815338153381
80024533803996180000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000050203245553359160000105338153381533815338153381
80024533804006180000479462516001016001080010343813014950300533805338043290256234335280183800201600205338078118002110910800101020050203244453359160000105338153381533815338153381
80024533804006180000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000050204244453359160000105338153381533815338153381
80024533803996180000479462516001016001080010343813004950300533805338043290256234335280010800201600205338078118002110910800101000050203245353359160000105338153381533815338153381
80024533804006180000479462516001016001080010343813004950300533805338043290256234335280010800201600205338078118002110910800101000050205245553359160000105338153381533815338153381
800245338040072680000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000050205245553359160000105338153381533815338153381
80024533804006180000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000050203245453359160000105338153381533815338153381
80024533804006180000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000050205243253359160000105338153381534355338153381
80024533804006180000479462516001016001080010343813004950300533805338043290270734335280010800201600205338078118002110910800101000050204244453359160000105338153421533815338153381