Firestorm: ADDS (sxtb, 32-bit) measurements

Code:

  adds w0, w0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	1	0	73	3	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	3	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1954	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  adds w0, w0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	1	0	0	0	0	61	10000	19868	25	20100	20100	10105	1305150	1	49	16955	20035	20035	18608	8	18735	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	19954	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19868	25	20100	20100	10105	1305150	1	49	16955	20035	20035	18608	7	18735	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	19954	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	0	0	0	0	0	61	10000	19868	25	20100	20100	10105	1305150	1	49	16955	20035	20035	18608	8	18735	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	19954	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19868	25	20100	20100	10105	1305150	1	49	16955	20035	20035	18608	8	18735	10105	10216	20232	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20177	20036	20036	20036	20036
10204	20035	150	0	0	0	21	264	61	10000	19862	25	20100	20181	10100	1305121	1	49	17002	20035	20035	18581	12	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	3483	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	12	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	4	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	4	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	4	41	4	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	4	41	4	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	4	41	4	4	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	4	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	4	41	2	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	12	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	4	41	4	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	61	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	4	41	3	4	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	346	10000	19862	25	20010	20010	10010	1305229	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	4	4	19930	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  adds w0, w1, w0, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	2	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	273	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	2	78	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	441	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	0	0	0	0	12	0	441	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	1	0	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	0	0	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	12	61	10000	19862	25	20010	20010	10010	1305229	1	49	17001	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	51	3	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	2	0	156	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	54	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20127	150	0	0	0	61	10000	19862	25	20034	20034	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	3	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	3	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	99	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  adds w0, w1, w2, sxtb
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	61	0	3	0	1	1	1	1320	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	90	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	227	0	0	0	61	10000	29899	67	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	18	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	147	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	102	0	1	1	1	1320	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	1	1	1	1320	16	29982	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	224	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	6	1270	14	33	13	13	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	126	1270	11	33	13	11	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	53	0	12	1270	13	33	13	13	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	3	1270	13	33	13	5	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30080	30080	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	87	1270	13	33	13	6	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	171	1270	12	33	13	13	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	120	1270	6	33	13	11	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	105	1270	11	33	11	12	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20022	10	9	10	20010	10010	0	0	0	144	1270	13	33	11	13	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	226	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	1	49	26955	0	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	87	1270	11	33	11	13	29959	30000	20010	30036	30036	30036	30036	30036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  adds w0, w1, w2, sxtb
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	1	6	1	1	1	1320	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	43	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	36	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	56	3	1	1	1	1320	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	27	6	1	1	1	1320	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	3	1	1	1	1320	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	82	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	61	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	53	0	1	1	1	1319	16	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	0	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	60	0	1	1	1	1319	16	29982	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20022	10	9	10	20010	10010	0	0	0	0	3	0	0	0	0	1270	4	33	4	4	29959	30000	20010	30036	30036	30036	30036	30219
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	34	0	3	0	0	1270	3	33	4	4	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	41	0	15	0	0	1270	4	33	4	4	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	35	0	0	0	0	1270	4	33	4	4	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	56	0	0	0	0	1270	5	33	4	4	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	26	0	0	0	0	1270	4	33	4	4	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	0	1270	3	33	4	4	29959	30000	20010	30036	30036	30036	30127	30036
20024	30035	225	0	0	0	0	0	0	12	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1011	0	0	1270	4	33	4	5	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	0	0	0	61	10006	29891	25	30010	30010	20010	1956289	1	49	27001	30035	30081	27438	8	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	1	0	3	0	0	1270	4	33	4	4	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	0	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	36	0	0	1270	4	33	4	4	29959	30000	20010	30036	30036	30036	30036	30036

Test 6: throughput

Count: 8

Code:

  adds w0, w8, w9, sxtb
  adds w1, w8, w9, sxtb
  adds w2, w8, w9, sxtb
  adds w3, w8, w9, sxtb
  adds w4, w8, w9, sxtb
  adds w5, w8, w9, sxtb
  adds w6, w8, w9, sxtb
  adds w7, w8, w9, sxtb

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	53449	400	0	0	0	0	0	28	80013	48791	29	160137	160218	80176	3441890	1	49	50334	53413	53414	43345	3024	8	43355	80176	80288	160376	53414	83	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5124	0	16	0	0	53411	160037	80100	53415	53415	53415	53415	53415
80204	53414	400	0	0	0	9	0	28	80013	48791	29	160137	160137	80176	3441890	1	49	50334	53414	53414	43345	2909	8	43355	80176	80288	160376	53414	39	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5124	0	16	0	0	53411	160037	80100	53415	53415	53415	53648	53415
80204	53414	400	0	0	0	0	0	220	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	79	6	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53458	400	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53467	53411	53411	53411
80204	53410	400	0	0	0	15	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53458	400	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	5110	1	24	1	1	53390	160000	80100	53411	53411	53411	53411	53411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	53384	399	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	7	24	4	12	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	6	24	5	3	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	48	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	24	5	5	53360	160000	80010	53381	53381	53609	53381	53381
80024	53380	400	0	0	0	0	346	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53430	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	24	4	9	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	24	6	6	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	11	24	6	5	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	24	11	4	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	11	24	11	6	53360	160000	80010	53381	53438	53438	53438	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	6	24	3	10	53360	160000	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	24	5	11	53360	160000	80010	53381	53381	53381	53381	53381

ADDS (sxtb, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations