Firestorm: NEGS (register, 32-bit) measurements

Code:

  negs w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	220	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	2	62	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	1000	1035	40	1	1	1001	1000	0	77	4	27	4	4	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  negs w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	10200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	4	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	1	0	0	0	0	0	0	145	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	0	0	0	0	0	251	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	2	0	1	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	10020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  negs w0, w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	251	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	20224	20080	64	1	1	20201	100	99	100	20100	10100	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	15	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1319	16	20045	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	20224	20035	64	1	1	20201	100	99	100	20100	10100	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	355	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	13	27	0	13	5	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	12	27	0	13	11	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	13	27	0	12	11	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	13	27	0	13	11	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	231	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	13	27	0	13	6	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	12	27	0	5	13	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	10	27	0	11	13	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	189	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	13	27	0	13	11	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	13	27	0	11	13	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	103	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	20020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	5	27	0	10	13	20003	20000	20010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  negs w0, w8
  negs w1, w8
  negs w2, w8
  negs w3, w8
  negs w4, w8
  negs w5, w8
  negs w6, w8
  negs w7, w8

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26761	200	60	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	1	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	39	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5132	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16719	3	16719	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	15	0	35	25	80100	80163	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	1	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	1	19	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	2	19	1	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	6	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16710	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	2	19	2	1	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	2	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	35	25	80100	80100	80100	400500	49	23655	0	26735	26735	16672	3	16690	80100	80200	80200	26735	39	1	1	80201	100	99	100	80100	100	0	0	5110	1	19	2	2	26731	80000	80100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26722	200	0	3	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	13	18	6	8	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	4	18	5	7	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	5	18	12	6	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	15	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	920	5020	0	0	6	18	6	6	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	24	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	3	18	5	11	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	56	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	6	18	4	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	5	18	11	6	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	4	18	6	6	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26799	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	3	5020	0	0	5	18	4	5	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	35	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	0	3	16683	80010	80020	80020	26705	39	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	5	18	5	11	26702	80000	80010	26706	26706	26706	26706	26706

NEGS (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations