Firestorm: LDRSB (register, uxtw, 32-bit) measurements

Code:

  ldrsb w0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	1	1	1	0	1	0	41	36	1	0	1	374	2	18	18	11	25	1000	1000	1000	14838	1	399	399	222	3	257	1000	1000	2000	399	82	1	1	1001	1000	1000	1	1019	20	42	1057	1	0	59	1038	6	1	57	42	18	1	73	1	16	1	1	396	9	9	2	1000	400	400	400	399	400
1004	399	3	1	1	1	1	1	0	65	0	1	0	3	384	2	18	18	16	25	1000	1000	1000	15360	1	398	399	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	1	1019	20	42	1057	0	2	59	1038	6	1	56	42	19	0	73	1	16	1	1	395	9	9	2	1000	399	400	400	400	399
1004	399	3	1	1	0	0	1	0	64	0	1	0	3	384	2	18	18	16	25	1000	1000	1000	15375	1	399	399	221	3	256	1000	1000	2000	399	82	1	1	1001	1000	1000	0	1021	22	41	1058	1	1	59	1038	6	1	57	42	19	0	73	1	16	1	1	395	9	9	2	1000	399	400	400	400	400
1004	399	2	1	1	1	0	0	0	65	0	1	0	2	384	2	18	18	16	25	1000	1000	1000	15318	1	399	399	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1019	21	42	1057	1	1	59	1038	6	1	57	41	19	0	73	1	16	1	1	396	9	9	2	1000	400	400	399	400	400
1004	399	2	1	0	0	0	0	0	65	0	1	0	3	383	2	18	18	16	25	1000	1000	1000	15362	1	398	399	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1019	21	42	1057	1	0	59	1038	6	1	57	42	19	0	73	1	16	1	1	395	9	9	2	1000	399	400	399	400	400
1004	399	2	1	0	0	0	0	0	65	0	1	0	2	383	1	18	18	16	25	1000	1000	1000	15362	1	442	398	221	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1020	21	42	1057	0	0	59	1038	6	1	57	42	19	2	73	1	16	1	1	396	9	9	2	1000	399	399	400	400	400
1004	399	3	1	0	1	0	0	0	65	0	1	0	2	384	2	18	18	15	25	1000	1000	1000	15357	1	399	399	222	3	256	1000	1000	2000	398	81	1	1	1001	1000	1000	0	1020	20	42	1057	0	1	59	1038	6	1	57	42	19	0	73	1	16	1	1	395	9	9	2	1000	399	400	400	400	400
1004	399	3	1	1	0	0	0	0	65	0	0	0	3	384	2	18	18	15	25	1000	1000	1000	15334	1	398	400	221	3	257	1000	1000	2000	398	84	1	1	1001	1000	1000	0	1019	21	42	1057	1	0	59	1038	6	1	56	42	19	1	73	1	16	1	1	396	9	9	2	1000	400	399	400	399	400
1004	399	2	1	0	1	0	0	0	65	0	1	0	3	384	2	18	18	16	25	1000	1000	1000	15362	1	399	399	221	3	257	1000	1000	2000	399	82	1	1	1001	1000	1000	0	1019	20	42	1057	0	1	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	9	9	2	1000	400	399	400	400	400
1004	399	3	1	0	1	0	0	0	65	0	1	0	3	384	2	18	18	16	25	1000	1000	1000	15318	1	399	399	228	3	257	1000	1000	2000	399	81	1	1	1001	1000	1000	0	1020	20	42	1057	1	2	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	9	9	2	1000	400	399	400	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70056	524	1	0	0	1	1	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616041	3341470	49	66955	0	70051	70035	64650	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	0	1	71	1	1	69814	30003	10	0	13	10000	30100	70052	70052	70095	70052	70055
40204	70035	525	0	0	0	0	1	0	70020	69782	59710	25	40104	30103	10000	30100	10000	616014	3342254	49	66971	0	70051	70051	64631	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	2610	0	1	71	1	1	69814	30003	10	0	10	10000	30100	70052	70036	70052	70052	70036
40204	70051	524	0	0	0	1	1	0	70020	69782	59710	25	40100	30103	10000	30100	10000	616014	3342254	49	66971	0	70035	70035	64647	3	64957	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	3	10000	1	1	0	0	2610	0	1	71	1	1	69818	30003	0	10	13	10000	30100	70052	70052	70052	70037	70052
40204	70051	525	0	0	0	3	0	0	70020	69783	59710	25	40104	30103	10001	30100	10000	616014	3342254	49	66971	0	70051	70035	64647	3	64938	40100	30200	10000	60200	20000	70072	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	3	10000	1	0	0	0	2610	0	1	71	1	1	69874	30003	10	13	10	10000	30100	70052	70036	70055	70052	70151
40204	70051	525	0	0	0	1	1	0	70122	69764	59710	25	40100	30100	10001	30100	10000	616175	3342398	49	66956	0	70035	70035	64714	3	64954	40100	30200	10000	60200	20000	70137	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	0	1	71	1	1	69814	30003	13	0	10	10000	30100	70052	70052	70036	70036	70052
40204	70079	524	0	0	0	1	0	1	70036	69764	59695	25	40104	30100	10000	30100	10000	616014	3341470	49	66974	0	70051	70035	64647	3	64938	40310	30200	10000	60200	20000	70142	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10003	0	0	0	10000	0	1	0	0	2610	0	2	71	1	1	69814	30003	0	0	0	10000	30100	70055	70052	70052	70036	70036
40204	70051	524	0	0	0	1	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616175	3341518	49	66971	0	70035	70051	64631	3	64938	40100	30200	10000	60200	20000	70084	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	2610	1	1	71	1	1	69814	30000	10	0	13	10000	30100	70055	70036	70055	70036	70093
40204	70051	525	0	0	0	1	0	0	70077	69785	59710	25	40104	30100	10001	30100	10000	616014	3342254	49	66955	0	70051	70035	64647	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	2610	0	1	71	1	1	69798	30003	0	10	10	10000	30100	70036	70055	70052	70055	70052
40204	70035	524	0	0	0	1	0	1	70020	69764	59695	25	40104	30103	10001	30100	10000	616014	3342254	49	66971	0	70051	70051	64647	3	64957	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	0	1	71	1	1	69798	30003	0	13	10	10000	30100	70052	70095	70036	70052	70036
40204	70053	524	0	0	0	1	0	1	70426	69812	59713	25	40104	30103	10003	30562	10051	618446	3341566	49	67411	0	70558	70573	64797	3	64954	40501	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	3	10000	0	1	0	0	2634	0	1	87	1	1	69817	30029	10	13	13	10000	30100	70055	70052	70036	70036	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	0	0	1	1	0	1	0	70032	69728	59706	25	40014	30010	10002	30010	10000	617068	3342062	0	49	66955	70047	70047	64653	3	64976	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	2520	0	1	71	2	1	69810	30000	0	0	6	10000	30010	70048	70051	70036	70048	70048
40024	70035	525	0	0	0	1	0	1	0	70032	69728	59695	25	40014	30013	10001	30010	10000	616982	3341470	0	49	66967	70047	70047	64665	3	65062	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	2520	0	1	71	1	1	69813	30003	0	0	6	10000	30010	70036	70048	70048	70036	70048
40024	70035	524	0	0	0	0	0	0	0	70035	69760	59706	25	40014	30013	10001	30010	10000	616952	3341470	0	49	66970	70050	70050	64665	3	65032	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	0	2520	0	1	71	1	1	69813	30012	6	0	0	10000	30010	70048	70048	70048	70048	70036
40024	70047	525	0	0	0	0	0	1	0	70020	69728	59706	25	40010	30010	10000	30161	10000	616952	3342206	0	49	66970	70035	70047	64665	3	65005	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	2520	0	1	17	1	2	69810	30003	0	6	6	10000	30010	70048	70048	70048	70048	70036
40024	70035	524	0	0	1	1	0	1	0	70020	69728	59706	25	40010	30010	10001	30010	10000	616952	3342062	0	49	66967	70035	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	0	0	0	2520	0	1	71	1	1	69813	30003	0	6	0	10000	30010	70036	70048	70048	70036	70048
40024	70047	525	0	0	0	349	0	1	0	70020	69743	59695	25	40014	30013	10001	30010	10000	616952	3341470	0	49	66967	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	0	1	0	2520	0	1	71	1	1	69810	30003	6	6	0	10000	30010	70036	70048	70051	70051	70048
40024	70047	524	0	0	0	43	0	1	0	70020	69743	59695	25	40014	30010	10001	30010	10000	616952	3342062	0	49	66955	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	2520	0	1	71	1	1	69798	30003	9	6	6	10000	30010	70051	70048	70048	70036	70048
40024	70035	524	0	0	0	24	0	1	0	70032	69728	59706	25	40014	30013	10001	30010	10000	617068	3342062	0	49	66955	70047	70047	64665	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	4	0	0	10000	1	1	0	2520	0	1	105	1	1	69800	30003	0	6	6	10000	30010	70317	70053	70048	70054	70050
40024	70047	524	0	1	0	28	352	1	0	70020	69731	59753	25	40014	30010	10000	30010	10000	617095	3341470	0	49	66967	70050	70047	64704	3	64974	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	4	0	6	10000	1	1	0	2520	0	1	71	1	1	69813	30003	0	6	9	10000	30010	70036	70048	70048	70048	70036
40024	70035	524	0	1	1	300	0	1	0	70035	69728	59709	25	40014	30013	10001	30010	10000	616952	3341470	0	49	66967	70047	70049	64667	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	2520	0	1	71	2	1	69813	30000	6	0	6	10000	30010	70036	70036	70036	70048	70316

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	0	1	1	70035	69764	59695	25	40104	30100	10002	30100	10000	616175	3342206	0	49	66955	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	0	0	6	10000	30100	70048	70048	70051	70048	70036
40204	70047	524	0	0	1	0	70032	69735	59695	25	40104	30100	10001	30100	10000	616015	3342062	1	49	66955	70035	70035	64631	3	64964	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	3	10000	1	1	0	0	2610	1	71	1	1	69821	30003	0	6	0	10000	30100	70036	70048	70048	70036	70048
40204	70038	525	0	0	1	0	70020	69764	59706	25	40104	30103	10001	30100	10051	618624	3345259	0	49	66967	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	0	10000	0	1	0	0	2610	1	71	1	1	69813	30003	6	6	6	10000	30100	70036	70048	70048	70048	70048
40204	70047	524	0	0	1	0	70032	69735	59695	25	40100	30100	10001	30100	10000	616175	3342062	0	49	66955	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	0	0	0	2610	1	71	1	1	69810	30003	6	6	0	10000	30100	70036	70036	70051	70051	70036
40204	70035	525	0	0	1	0	70032	69764	59706	25	40100	30103	10001	30100	10000	616015	3342062	0	49	66955	70035	70047	64646	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	3	10000	1	1	0	0	2610	1	71	1	1	69810	30003	0	6	9	10000	30100	70049	70051	70048	70048	70048
40204	70047	524	0	0	1	1	70032	69735	59695	25	40104	30100	10000	30100	10000	616015	3342062	0	49	66967	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69813	30003	6	0	6	10000	30100	70036	70036	70036	70051	70051
40204	70035	525	0	0	10	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66967	70050	70047	64643	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	0	0	0	2610	1	71	1	1	69813	30003	0	9	9	10000	30100	70036	70036	70048	70048	70051
40204	70050	525	0	0	1	0	70020	69735	59706	25	40104	30100	10000	30100	10000	616015	3342062	0	49	66971	70038	70035	64631	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	0	1	0	0	2610	1	71	1	1	69813	30003	0	0	9	10000	30100	70036	70048	70051	70051	70048
40204	70050	525	0	0	1	1	70032	69735	59709	25	40104	30103	10001	30100	10000	616005	3341470	0	49	66970	70050	70035	64646	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70048	70048	70048	70036	70048
40204	70035	524	0	1	6	0	70035	69781	59706	25	40100	30103	10001	30100	10000	616005	3341470	1	49	63937	70050	70050	64643	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	1	0	2610	1	71	1	1	69810	30012	0	0	6	10000	30100	70051	70048	70051	70048	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70143	543	0	1	1	0	1	0	0	0	70039	69791	59715	25	40010	30013	10001	30010	10000	616991	3342254	0	49	66971	0	70054	70054	64672	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	0	1	0	2520	3	71	4	2	69798	30003	0	10	13	10000	30010	70055	70055	70136	70085	70036
40024	70035	524	0	0	0	0	0	0	0	0	70036	69775	59725	25	40014	30013	10001	30010	10000	617068	3342398	0	49	66971	0	70035	70051	64669	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	1	0	10000	1	0	1	0	2520	2	71	4	4	69814	30000	10	10	13	10000	30010	70036	70036	70052	70145	70055
40024	70051	524	0	0	0	0	1	0	1	0	70039	69775	59763	25	40014	30010	10000	30010	10000	616991	3342398	0	49	66974	0	70051	70054	64672	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	1	0	2520	3	71	2	2	69817	30000	13	0	13	10000	30010	70055	70055	70052	70134	70055
40024	70054	524	0	0	0	0	1	0	1	0	70039	69775	59721	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66955	0	70051	70051	64669	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	1	0	2520	2	71	4	4	69814	30003	13	13	13	10000	30010	70036	70055	70052	70129	70036
40024	70035	524	0	0	0	0	1	0	0	0	70020	69775	59766	25	40014	30013	10001	30010	10000	617018	3342398	0	49	66955	0	70035	70054	64672	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	0	0	0	2520	3	71	2	2	69817	30000	13	13	0	10000	30010	70055	70036	70052	70159	70055
40024	70051	525	0	0	0	0	2	0	0	0	70020	69812	59713	25	40014	30013	10001	30010	10000	617018	3342398	0	49	66977	0	70054	70054	64672	7	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	0	0	0	0	2520	4	71	2	2	69817	30003	0	13	10	10000	30010	70036	70036	70052	70141	70036
40024	70054	524	0	0	0	0	1	0	1	0	70020	69743	59760	25	40014	30013	10000	30010	10000	617018	3342398	0	49	66974	0	70054	70035	64653	0	3	64979	40010	30215	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	0	1	0	2520	4	71	4	2	69817	30003	10	13	13	10000	30010	70052	70055	70052	70130	70055
40024	70035	524	0	0	0	0	1	0	0	0	70020	69775	59743	25	40014	30013	10001	30010	10000	617018	3341470	0	49	66971	0	70035	70054	64672	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	0	10000	1	0	1	0	2520	2	71	4	3	69817	30003	13	10	13	10000	30010	70055	70055	70052	70152	70036
40024	70035	524	0	0	0	0	6	0	0	0	70039	69775	59738	25	40014	30013	10001	30010	10000	617018	3342398	0	49	66974	0	70054	70054	64653	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	1	0	10000	1	0	1	0	2520	4	71	3	4	69817	30003	10	10	0	10000	30010	70144	70055	70083	70052	70052
40024	70051	524	0	0	0	0	1	0	0	0	70020	69775	59799	25	40014	30010	10000	30010	10000	617018	3342398	0	49	66974	0	70054	70035	64672	0	3	64979	40010	30020	10000	60020	20000	70059	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	10000	1	0	1	0	2520	2	71	2	2	69817	30003	13	13	13	10000	30010	70055	70055	70052	70127	70055

Test 4: throughput

Count: 8

Code:

  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26722	200	0	1	0	41	1	0	1	26716	17	0	30	17	25	80100	100	80000	100	80016	500	1172500	49	23652	26731	26716	16662	6	16683	80114	200	80024	200	160048	26815	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	0	80000	0	35	80035	6	1	0	39	1	1	1	5118	0	16	0	0	26704	6	6	4	80000	100	26723	26723	26708	26723	26728
80204	26722	200	0	1	0	41	1	0	1	26712	2	18	18	12	25	80100	100	80000	100	80015	500	1166596	49	23627	26722	26722	16650	6	16659	80115	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80000	1	0	80039	6	1	35	39	1	1	1	5118	0	16	0	0	26722	6	6	4	80000	100	26723	26723	26723	26723	26708
80204	26707	200	0	0	0	41	0	0	1	26707	0	0	18	11	25	80100	100	80000	100	80015	500	1167875	49	23642	26707	26722	16635	6	16674	80114	200	80024	200	160048	26723	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80035	0	35	80000	6	1	35	39	1	1	1	5118	0	16	0	0	26719	6	0	2	80000	100	26723	26723	26723	26723	26723
80204	26727	200	0	0	0	41	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80014	500	1166596	49	23642	26722	26707	16635	6	16674	80114	200	80024	200	160048	26726	71	1	1	80201	100	99	100	80000	100	80000	0	100	80134	39	0	80035	0	39	80035	0	0	35	39	1	1	1	5118	0	16	0	0	26719	6	6	0	80000	100	26723	26723	26723	26728	26728
80204	26722	200	0	1	1	41	1	0	1	26707	2	0	12	0	25	80100	100	80000	100	80014	500	1159814	49	23642	26707	26722	16650	6	16674	80114	200	80024	200	160048	26861	81	1	1	80201	100	99	100	80000	100	80000	0	100	80000	58	0	80051	1	54	80054	6	1	54	43	1	1	1	5118	0	16	0	0	26704	6	6	2	80000	100	26723	26723	26723	26708	26728
80204	26722	200	0	0	0	45	0	0	1	26707	2	18	18	12	25	80100	100	80000	100	80015	500	1159814	49	23642	26722	26722	16650	6	16674	80114	200	80024	200	160048	26724	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80035	0	35	80035	6	1	35	43	1	1	1	5118	0	16	0	0	26724	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26707	200	0	0	0	0	0	0	1	26707	2	18	18	11	25	80100	100	80000	100	80014	500	1167875	49	23627	26722	26722	16650	6	16659	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80035	0	42	80035	6	1	35	39	1	1	1	5118	0	16	0	0	26719	6	6	0	80000	100	26708	26723	26708	26723	26723
80204	26707	200	0	1	1	0	1	0	1	26707	2	0	12	12	25	80100	100	80000	100	80015	500	1166596	49	23642	26707	26707	16650	6	16674	80114	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	0	80035	1	35	80000	6	0	0	43	1	1	1	5118	0	16	0	0	26704	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26707	200	0	0	0	0	1	0	2	26707	0	12	0	12	25	80100	100	80000	100	80014	500	1167303	49	23642	26722	26727	16650	6	16674	80115	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	0	80000	0	35	80035	6	1	35	39	1	1	1	5118	0	16	0	0	26728	6	6	3	80000	100	26732	26733	26733	26733	26732
80204	26731	200	0	0	0	25	1	0	0	26707	2	18	0	12	25	80100	100	80000	100	80016	500	1165856	49	23642	26722	26722	16650	6	16659	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80035	0	35	80035	6	1	35	39	1	1	1	5118	0	16	0	0	26719	0	6	2	80000	100	26726	26724	26726	26723	26726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	0	0	1	0	1	1	0	0	0	0	1	0	1	26712	2	12	7	127	25	80010	10	80000	10	80000	50	1168843	49	23628	26727	26727	16822	3	16707	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	39	80000	6	1	39	44	0	0	5020	2	17	0	4	2	26728	14	10	4	80000	10	26717	26730	26739	26733	26709
80024	26728	200	0	0	0	0	0	0	0	0	0	0	1	0	1	26693	2	12	0	20	25	80010	10	80000	10	80000	50	1167907	49	23656	26737	26736	16682	3	16695	80010	20	80000	20	160000	26714	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80038	0	0	0	38	80039	6	1	39	43	0	0	5020	4	16	0	4	2	26724	0	10	7	80000	10	26732	26730	26740	26747	26729
80024	26731	200	0	0	0	0	0	0	0	0	45	0	1	0	1	26693	2	0	7	21	25	80010	10	80000	10	80000	50	1165304	49	23656	26715	26714	16681	3	16716	80010	20	80000	20	160000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	0	80000	6	1	38	44	0	0	5020	4	16	0	2	4	26725	10	10	4	80000	10	26840	26748	26826	26750	26737
80024	26736	200	1	1	1	1	0	0	0	0	21	0	0	0	0	26721	3	7	7	21	25	80010	10	80000	10	80000	50	1166886	49	23648	26727	26729	16676	3	16711	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	80058	0	0	0	60	80040	6	1	19	43	19	1	5020	4	16	0	4	2	26734	0	13	5	80000	10	26842	26743	26786	26719	26728
80024	26731	200	0	0	0	0	0	0	0	0	45	0	1	0	0	26712	2	12	0	26	25	80010	10	80000	10	80000	50	1166896	49	23651	26727	26708	16676	3	16711	80010	20	80000	20	160000	26727	56	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	42	80039	6	1	39	44	0	0	5020	2	16	0	3	4	26728	10	10	4	80000	10	26850	26742	26737	27308	26719
80024	26737	200	1	0	1	1	0	0	0	0	67	0	0	0	2	26721	3	0	7	168	25	80010	10	80000	10	80000	50	1167201	49	23651	26708	26727	16672	3	16707	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	80058	0	0	1	60	80040	6	0	58	43	19	0	5020	2	16	0	4	4	26733	13	0	5	80000	10	26738	26852	26710	26739	26732
80024	26728	200	0	0	0	0	0	0	0	0	45	0	1	0	1	26712	2	1	7	20	25	80010	10	80000	10	80000	50	1167298	49	23635	26736	26736	16659	3	16695	80010	20	80000	20	160000	26737	113	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	39	80039	6	0	0	43	0	0	5020	4	16	0	4	2	26725	14	10	0	80000	10	26753	26739	26751	26750	26738
80024	26737	201	1	0	0	1	0	0	0	0	66	0	0	0	3	26721	3	7	7	16	25	80010	10	80000	10	80000	50	1168843	49	23647	26728	26727	16672	3	16688	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	43	80059	0	1	0	61	80040	6	1	59	43	19	3	5020	3	16	0	4	4	26733	13	13	5	80000	10	26737	26863	26738	26731	26732
80024	26867	200	0	0	1	0	0	0	1	0	210	88	0	0	1	26874	2	12	7	175	25	80010	10	80000	10	80000	50	1167219	49	23635	26719	26714	16660	3	16716	80010	20	80000	20	160000	26719	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80000	0	2	0	42	80169	6	1	39	43	0	0	5020	4	24	0	4	2	26728	0	10	0	80000	10	26737	26737	26768	26741	26746
80024	26737	201	1	1	1	1	0	0	0	0	67	0	1	0	3	26700	0	7	7	18	25	80010	10	80000	10	80000	50	1166750	49	23651	26731	26731	16652	3	16708	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	19	45	80060	0	0	1	61	80041	6	1	59	0	19	1	5020	2	16	0	4	2	26734	13	13	5	80000	10	26788	26749	26733	26804	26738

LDRSB (register, uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations