Firestorm: PACIA measurements

Code:

  pacia x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	104	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7107	870	1	1	1001	1000	0	0	0	3	0	73	2	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	63	0	104	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	70	12	82	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	3	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	0	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	3	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	1	3	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	1	0	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	1	0	0	73	1	85	1	1	6789	1003	0	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	1	0	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7070
1004	7029	70	0	96	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	1	3	0	73	1	85	1	1	6789	1000	0	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  pacia x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0f	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	570	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	0	0	0	0	103	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70677	70030	70030	70030	70030
10204	70029	619	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69833	10100	10100	70030	70030	70030	70030	70030
10204	70029	619	0	0	0	0	0	0	0	726	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	9	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	103	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	1	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10230	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	710	0	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	616	0	0	0	0	0	21	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	71331	71292	68911	154	69502	10920	11287	22684	71210	870	33	1	10021	10	9	10010	2	0	1	62768	2	1012	4	356	0	5	5	70600	10113	0	10010	71293	71367	71362	70813	70030
10024	70029	675	0	0	0	0	1	12	0	943	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	36	0	640	2	79	0	2	2	69905	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	655	0	0	0	0	0	0	0	213	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	0	2	2	69805	10010	0	10010	70030	70030	70055	70030	70030
10024	70029	657	0	0	0	0	0	12	0	103	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	0	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70068	655	0	0	0	0	0	0	0	285	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	0	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	615	0	0	0	0	0	0	0	66	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	3	0	640	2	79	0	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	621	0	0	0	0	0	12	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	0	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	3	79	0	2	3	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	0	251	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20138	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	0	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030
10024	70029	655	0	0	0	0	0	0	0	726	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	0	2	2	69805	10010	0	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  pacia x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	697	0	0	0	0	0	12	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76994	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	2	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	750	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40362	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	696	0	0	0	0	0	0	0	0	103	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80068	144	1	1	30201	100	99	30100	0	0	0	0	0	2	0	0	0	0	1931	1	72	1	3	79794	20100	30100	80030	80076	80030	80030	80030
30204	80029	749	0	0	0	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	1	72	2	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	749	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20264	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	1	0	0	0	0	726	69799	45	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	3	0	3	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80074	749	0	0	0	0	0	12	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76188	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	695	0	0	0	0	0	12	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80074	144	1	1	30201	100	99	30100	0	0	0	0	0	0	3	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	699	0	0	0	0	0	0	0	0	61	69790	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20280	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80071	80030	80030	80030	80030

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5e	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	80029	696	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	0	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	89	69799	25	20020	20020	20020	4952048	0	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	3	0	3	0	0	1890	2	72	0	4	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	438	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	133	76854	22072	22603	45402	81460	144	33	1	30021	10	9	30010	2	0	0	1	0	67970	0	0	2224	3	264	0	5	2	80365	20010	30010	81290	81053	81110	81098	81105
30024	80853	754	1	12	0	0	0	0	1331	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	1	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	487	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	3	76199	20020	20020	40020	80079	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80078	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20015	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	135	0	0	103	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	1	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	145	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	714	0	0	0	0	0	0	103	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	3	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	0	0	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	1890	2	72	0	2	2	79803	20010	30010	80030	80030	80030	80030	80030

Test 4: throughput

Count: 8

Code:

  pacia x0, x8
  pacia x1, x8
  pacia x2, x8
  pacia x3, x8
  pacia x4, x8
  pacia x5, x8
  pacia x6, x8
  pacia x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80041	698	0	0	0	0	117	0	0	742	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	63	0	3	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	744	0	0	0	0	0	0	0	77	25	80221	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160264	80035	164	1	1	80201	100	99	80100	0	0	0	0	36	0	3	0	0	5110	2	33	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	12	0	0	91	25	80200	80200	80222	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	31	0	0	0	0	5110	2	25	2	2	80067	80100	80100	80082	80036	80036	80036	80036
80204	80035	699	0	0	0	0	30	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69984	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	59	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80081	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	3	0	6	0	0	5110	2	25	3	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80080	699	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	5	0	3	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	78	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80222	80200	160312	80035	164	1	1	80201	100	99	80100	0	0	0	0	2	0	3	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	12	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	4	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	700	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	2	0	3	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	699	1	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	2	0	1	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	699	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	0	5	25	3	2	80024	80010	80010	80081	80173	80036	80036	80036
80024	80035	702	0	0	83	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	0	3	25	3	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	703	0	0	91	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	0	2	25	2	3	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	0	3	25	3	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	694	0	0	35	43	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	0	3	25	3	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5051	0	2	25	2	4	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	700	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80064	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	3	6	0	5020	0	4	25	3	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	0	2	25	2	3	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	697	0	0	700	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	5020	0	3	25	3	2	80024	80010	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	700	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	4	0	2	0	0	5020	0	2	25	2	3	80024	80010	80010	80036	80036	80036	80036	80036

PACIA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations