Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (sxtx, 64-bit)

Test 1: uops

Code:

  subs x0, x0, x1, sxtx
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103580061917251000100010006225011035103580538821000100020001035401110011000073127119931000100010361036103610361036
1004103570061917251000100010006225001035103580538821000100020001035401110011000073127219931000100010361036103610361036
1004103570061917251000100010006225001035103580538821000100020001035431110011000073127119931000100010361036103610361036
10041035805461917251000100010006225001035103580538821000100020001035401110011000073127119931000100010361036103610361036
1004103570061917251000100010006225001035103580539091000100020001035401110011000073127119931000100010361036103610361036
1004103580061917251000100010006225011035103580538821000100020001035401110011000073127119931000100010361036103610361036
1004103580061917251000100010006225011035103580538821000100020001035401110011000073127119931000100010361036103610361036
1004103580061917251000100010006225011035103580538821000100020001035431110011000073127119931000100010361036103610361036
1004103580061917251000100010006225011035103580538821000100020001035401110011000073127119931000100010361036103610361036
1004103580961917251000100010006225011035103580538821000100020001035401110011000073127119931000100010361036103610361036

Test 2: Latency 1->2

Code:

  subs x0, x0, x1, sxtx
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035750005286199202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000071012712999510000101001003610036100361003610036
1020410035760001596199202510100101001010064715214969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036
102041003575000020699202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000171012711999510000101001003610036100361003610036
102041003575000126199202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357500036199202510100101001010064715214969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036
102041003575000126199202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357500006199202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036
102041003575000060999202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357500006199202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036
10204100357500006199202510100101001010064715204969551003510035865638732101001020020200100354011102011009910010100100000071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357506199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064032722999710000100101003610036100361003610036
100241003575028199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036
100241003575026999182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036
100241003575067299182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036
100241003575054999182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036
10024100357506199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036
100241003575072899182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036
10024100357506199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010102364022722999710000100101003610036100361003610036
10024100357506199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036
10024100357506199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100064022722999710000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  subs x0, x1, x0, sxtx
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357552861992025101001010010100647152149695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035750611992025101001010010100647152049695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036101291008310036
102041003575061992025101001010010100647152149695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035756361992025101001010010100647152049695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035756361992025101001010010100647152149695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
102041003575361992025101001010010100647152049695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
102041003576061992025101001010010100647152149695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
102041003576061992025101001010010100647152149695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
102041003576061992025101001010010100647152049695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036
1020410035750189992025101001010010100647152049695510035100358656387321010010200202001003540111020110099100101001000071022722999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024101787601013340826408619917931008010078100926491050497097101771017787112288521025910310205961017740411002110910100101022200225050692451851006810067100101017710179100361017710178
10024102237600013340526401249920931001010079102586491251497099101771017887112387541025910310207901017840411002110910100101002001016382679455891013110068100101017810165101791017910178
10024101767600111239926418499917941010010102102586491261497053101761017687112388601025710309205981013140411002110910100101000201216630694527481005010022100101017810179100361013110191
10024100837601103101760103991870100561001010176648983049705010131101318678388081025810214204081012940311002110910100101000011216630695342661006610045100101016810130100361013210132
100241008276300021026406199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100000000064032733999710000100101003610036100361003610036
1002410035750000000006199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100000000064032733999710000100101003610036100361003610036
1002410035750000000006199182510010100101001064724604969551003510035867838754100101002020020100354011100211091010010100000000064032733999710000100101003610036100361003610036
10024100357500000000073999182510010100101001064724604969551003510035867838754100101002020020100354011100211091010010100000000064032733999710000100101003610036100361003610036
1002410035750000000006199182510010100101001064724614969551003510035867838754100101002020020100354011100211091010010100000000064032733999710000100101003610036100361003610036
1002410035750000000006789918411001010010100106472460496955100351003586783875410010100202002010035401110022109101001010000000150640327331005210000100101003610036100361003610036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, x2, sxtx
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)0318191e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202042003515000510611993025201002010020112129723314916955200352003517425717486201122022430236200356411202011009910020100101000001111319016002001220000201002003620036200362003620036
20204200351500000841993025201002010020112129723314916955200352003517425817486201122022430236200356411202011009910020100101002031111320016002001220000201002003620036200362003620082
202042003515000003491993025201002010020193129723314916955200352003517425817485201122022430236200356411202011009910020100101000001111320016002001220000201002003620036200362003620036
202042003515010003621993025201002012420112129723314916955200352003517425717485201122022430236200356411202011009910020100101000001111320016002001220000201002003620036200362003620036
202042003515000001031993025201002010020112129723314916955200352003517425817486201122022430236200356411202011009910020100101000001111319016002001220000201002003620036200362003620036
20204200351500000611993025201002010020112129723314916955200352003517425717486201122022430236200356411202011009910020100101000001111320016002001220000201002003620036200362003620036
20204200351500000611993025201002010020112129723314916955200352003517425717486201122022430236200826411202011009910020100101002001111319016002001220000201002003620036200362003620036
202042003515001181611993025201002012220112129723314916955200352003517425717485201122022430236200356411202011009910020100101000001111319116002001220000201002003620036200362003620036
2020420035150001204411993025201002010020112129723314916955200352003517425817486201122022430236200356411202011009910020100101000001111319016002001220000201002003620036200362003620036
202042003515000210611993025201002010020112129723314916955200352003517425717485201122022430236200356411202011009910020100101000101111319016002001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002420035150010819918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227221999520000200102003620036200362003620036
200242003515008219918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150010319918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227231999520000200102003620036200362003620036
200242003515006119918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150014519918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150035919918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010101270227231999520000200102003620036200362003620036
2002420035150027219918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227221999520000200102003620036200362003620036
200242003514906119918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227222004720000200102003620036200362003620036
20024200351500103319918252001020010200101297247491695520081200801742831750420010200203002020035641120021109102001010010001270227221999520000200102003620036200362003620036
200242003515006119918252001020010200101297247491695520035200351742831750420010200203002020035641120021109102001010010001270227221999520000200102003620036200362003620036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, x2, sxtx
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351502316119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010001111319162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174257174862011220224302362003564112020110099100201001010001111320162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174258174862011220224302362003564112020110099100201001010001111319162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174258174852011220224302362003564112020110099100201001010001111320162001220000201002003620036200362003620083
20204200351502706119930252010020100201121297233049169552003520035174257174862011220224302362008164212020110099100201001010001111320162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233049169552003520035174258174852011220224302362003564112020110099100201001010001111320162001220000201002003620036200362003620036
202042003515066119930252010020100201121297233049169552003520035174258174862011220224302362003564112020110099100201001010001111320162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233049169552003520035174258174852011220224302362003564112020110099100201001010001111320162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233049169552003520035174257174852011220224302362003564112020110099100201001010001111319162001220000201002003620036200362003620036
2020420035150876119930252010020100201121297233049169552003520035174258174862011220224302362003564112020110099100201001010011111320162001220022201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515000000036119918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270127321999520000200102003620036200362003620036
200242003515000000010519918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270227211999520000200102003620036200362003620036
200242003515000000012419918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270127121999520000200102003620036200362003620036
20024200351500000006119918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270127121999520000200102003620036200362003620036
20024200351500000006119918252001020034200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270127121999520000200102003620036200362003620036
20024200351500000006119918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270227211999520000200102003620036200362003620036
20024200351500000006119918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270327111999520000200102003620036200362003620036
20024200351500000008219918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001270227211999520000200102003620036200362003620036
20024200351500000006119918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001001101270127221999520000200102003620036200362003620036
200242003515000000060019918252001020010200101297247049169552003520035174283175042001020020300202003564112002110910200101001000001287227211999520000200102003620036200362003620036

Test 6: throughput

Count: 8

Code:

  subs x0, x8, x9, sxtx
  subs x1, x8, x9, sxtx
  subs x2, x8, x9, sxtx
  subs x3, x8, x9, sxtx
  subs x4, x8, x9, sxtx
  subs x5, x8, x9, sxtx
  subs x6, x8, x9, sxtx
  subs x7, x8, x9, sxtx
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426761200090352580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010000005110219222673180000801002673626736267362673626736
802042673520000352580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010000005110219222673180000801002673626736267362673626736
8020426735200015352580100801008010040050004923655267352673516672316690801008020016020026735391180201100991008010010010005110219222673180000801002673626736267362673626736
802042673520006352580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010000005110219222673180000801002673626736267362673626736
802042673520000352580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010000005110319222673180000801002673626736267362673626736
8020426735200318352580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010000005110219222673180000801002673626736267362673626736
802042673520000352580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010000005110219222673180000801002673626736267362673626736
802042673520000352580100801008010040050004923655267352673516672316690801008020016020026735391180201100991008010010000005110219222673180000801002673626736267362673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200160200267353911802011009910080100100005105110219222673180000801002673626736267362673626736
802042673520006352580100801008010040050014923655267352673516672316690801008020016020026735391180201100991008010010000005110219222673180000801002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)1e3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267202000000079258001080010800104000500049236252670526705166653166838001080020160020267053911800211091080010100310050206180262670280000800102670626706267062670626706
80024267052000000035258001080010800104000500049236252670526705166653166838001080020160020267053911800211091080010100000050202180262670280000800102670626706267062670626706
80024267052000000035258001080010800104000500049236252670526705166653166838001080020160020267053911800211091080010100000050206180262670280000800102670626706267062670626706
800242670520000000142258001080010800104000501049236252670526705166653166838001080020160020267053911800211091080010100000050202180222670280000800102670626706267062670626706
80024267052000000035258001080010800104000500149236252670526705166653166838001080020160020267053911800211091080010100000050202180622670280000800102670626706267062670626706
800242670520000000670258001080010800104000500049236252670526705166653166838001080020160020267053911800211091080010100002050202180362670280000800102670626706267062670626706
80024267052000000035258001080010800104000500049236252670526705166653166838001080020160020267053911800211091080010100000050202180262670280000800102670626706267062670626706
800242670520000000182258001080010800104000500049236252670526705166653166838001080020160020267053911800211091080010100000050202180262670280000800102670626706267062670626706
800242670520000000508258001080010800104000500149236252670526705166653166838001080020160020267053911800211091080010100000050202180222670280000800102670626706267062670626706
80024267052000000035258001080010800104000500049236252670526705166653166838001080020160020267053911800211091080010100000050202180362670280000800102670626706267062670626706