Firestorm: LDNP (64-bit) measurements

Code:

  ldnp x0, x1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	389	3	0	0	1	0	0	0	0	0	1	0	1	374	0	18	0	0	25	1000	1000	1000	14812	0	389	389	87	3	132	1000	2000	1000	399	35	1	1	1001	1000	1000	0	1021	20	42	1057	1	0	0	59	1038	6	1	57	42	19	1	73	1	16	1	1	386	1000	10	6	0	1000	1000	375	375	395	390	395
2004	389	3	0	0	0	0	0	0	0	0	1	0	3	384	2	0	18	15	25	1000	1000	1000	15358	0	381	381	96	3	115	1000	2000	1000	381	35	1	1	1001	1000	1000	1	1000	0	0	1039	0	0	0	39	1039	6	1	35	43	0	0	73	1	16	1	1	378	1019	9	9	2	1000	1000	399	399	399	400	382
2004	381	3	1	0	0	0	0	0	0	21	0	0	3	384	2	18	18	0	25	1000	1000	1000	15358	0	398	399	96	3	132	1000	2000	1000	399	35	1	1	1001	1000	1000	0	1021	19	0	1057	0	0	0	59	1037	6	0	57	42	19	0	73	1	16	1	1	371	1039	0	6	4	1000	1000	390	375	395	375	395
2004	389	2	0	0	0	0	0	0	0	45	0	0	0	359	0	0	12	16	25	1000	1000	1000	14846	0	394	394	92	3	127	1000	2000	1000	389	35	1	1	1001	1000	1000	0	1001	0	0	1035	0	0	0	39	1035	6	0	0	43	0	0	73	1	16	1	1	371	1039	10	0	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	0	0	0	0	0	45	0	0	3	366	0	18	18	16	25	1000	1000	1000	15358	0	398	398	97	3	115	1000	2000	1000	399	35	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	0	1000	6	0	0	0	0	0	73	1	16	1	1	386	1039	10	0	2	1000	1000	395	375	395	395	375
2004	394	3	0	0	0	0	0	0	0	45	1	0	2	359	0	0	12	16	25	1000	1000	1000	15014	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1019	20	0	1019	0	0	0	21	1000	6	1	19	42	19	1	73	1	16	1	1	386	1000	6	6	2	1000	1000	375	375	395	395	395
2004	374	3	0	0	0	0	1	0	0	0	0	0	2	366	2	0	0	16	25	1000	1000	1000	15358	0	398	398	97	3	131	1000	2000	1000	399	35	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	39	1035	6	1	35	0	0	0	73	1	16	1	1	391	1039	0	6	0	1000	1000	395	395	395	375	395
2004	394	3	0	0	0	0	1	0	0	45	0	0	2	379	2	12	0	11	25	1000	1000	1000	14812	0	374	374	92	3	107	1000	2000	1000	374	35	1	1	1001	1000	1000	0	1000	0	0	1039	0	1	0	39	1000	0	1	35	43	0	0	73	1	16	1	1	391	1000	0	6	4	1000	1000	395	395	395	395	377
2004	389	3	0	0	0	0	0	0	0	45	0	0	2	379	2	12	0	0	25	1000	1000	1000	15053	0	394	394	92	3	107	1000	2000	1000	374	35	1	1	1001	1000	1000	0	1020	20	42	1057	1	1	1	59	1038	0	1	57	0	19	1	73	1	16	1	1	387	1000	10	6	4	1000	1000	395	375	395	395	375
2004	389	3	0	0	0	0	1	1	0	45	0	0	2	359	0	18	12	0	25	1000	1000	1000	14075	0	394	374	72	3	107	1000	2000	1000	394	35	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	39	1000	0	1	40	0	0	0	73	1	16	1	1	396	1057	9	0	2	1000	1000	399	400	400	399	382

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp x0, x1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70056	525	1	1	1	0	0	0	0	2	0	1	0	1	70038	69711	59702	25	40108	30106	10002	30100	10000	613846	3342202	0	49	66973	0	70053	70053	63406	3	63713	40100	30200	20000	60200	10000	70053	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	0	1	7	10000	1	1	1	1	0	0	0	2610	2	64	1	1	69819	10001	30006	0	6	6	10000	40100	70149	70259	70433	70042	70154
50204	70053	524	1	0	0	0	0	0	1	2	0	0	0	1	70038	69718	59702	25	40108	30106	10001	30100	10000	613873	3342202	0	49	66973	0	70053	70053	63407	3	63713	40100	30200	20000	60200	10000	70055	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	0	2	0	4	10000	1	1	1	1	1	0	0	2610	1	78	2	1	69876	10001	30006	6	6	0	10000	40100	70054	70055	70059	70054	70054
50204	70053	525	1	1	1	1	0	0	0	2	0	1	0	1	70038	69718	59702	25	40108	30106	10002	30100	10000	613846	3342202	0	49	66961	0	70067	70422	63522	3	63713	40100	30200	20000	60200	10000	70054	37	5	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10003	0	0	1	4	10000	1	1	1	1	0	0	0	2610	1	64	1	1	69817	10001	30006	6	6	6	10000	40100	70054	70054	70054	70054	70054
50204	70053	525	1	0	0	0	0	0	0	2	0	0	0	0	70038	69718	59702	25	40108	30106	10002	30100	10000	613846	3342202	0	49	66973	0	70053	70053	63394	3	63713	40100	30200	20000	60200	10000	70053	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10010	2	1	10001	0	0	0	1	10000	1	1	1	1	1	0	0	2610	1	78	2	1	69820	10001	30003	6	6	6	10000	40100	70054	70054	70042	70054	70042
50204	70053	525	1	1	1	0	0	0	0	2	0	0	0	1	70038	69718	59702	25	40108	30106	10001	30100	10000	613846	3342202	0	49	66973	0	70041	70041	63394	3	63713	40100	30200	20000	60200	10000	70041	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10001	0	7	1	1	10000	1	1	0	1	2	0	0	2610	1	64	1	1	69818	10001	30003	6	0	6	10000	40100	70054	70054	70054	70054	70057
50204	70053	524	1	1	1	0	0	0	0	7	0	0	0	1	70026	69711	59704	25	40104	30106	10002	30100	10000	613646	3342202	0	49	66973	0	70041	70053	63394	3	63687	40100	30200	20000	60200	10000	70053	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	0	10001	0	0	1	1	10000	1	1	1	1	1	0	0	2610	1	64	1	1	69819	10001	30006	6	0	6	10000	40100	70054	70042	70177	70055	70058
50204	70043	524	1	0	1	1	1	0	0	2	0	1	0	1	70038	69718	59702	25	40104	30106	10002	30100	10000	613646	3341607	0	49	66973	0	70053	70046	63406	3	63713	40100	30200	20000	60200	10000	70041	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	2	0	10002	0	0	0	1	10000	1	1	1	1	1	0	0	2610	1	64	1	1	69820	10001	30003	0	6	6	10000	40100	70054	70042	70042	70054	70054
50204	70053	524	0	0	0	1	1	0	0	1	0	1	0	0	70020	69711	59694	25	40104	30103	10001	30100	10000	613756	3341906	0	49	66958	0	70047	70047	63400	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	2610	1	64	0	1	69810	10000	30000	6	6	6	10000	40100	70048	70048	70048	70036	70048
50204	70035	524	0	0	0	0	0	0	0	1	0	1	0	0	70032	69711	59694	25	40100	30103	10001	30100	10000	613756	3341906	1	49	66955	0	70035	70047	63388	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	2610	1	64	2	1	69812	10000	30003	6	0	6	10000	40100	70048	70048	70048	70049	70036
50204	70047	524	0	0	0	0	0	0	0	1	0	1	0	0	70032	69711	59694	25	40104	30103	10001	30100	10000	613756	3341906	0	49	66967	0	70047	70047	63400	3	63707	40100	30200	20000	60200	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	2610	0	64	1	1	69834	10000	30003	6	6	0	10000	40100	70048	70048	70048	70048	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70057	525	1	0	1	1	1	1	2	1	0	1	70042	69725	59710	25	40014	30016	10002	30010	10000	615508	3342686	49	66961	70060	70060	63429	3	63739	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	0	0	1	10000	1	1	0	1	1	0	2520	5	64	0	8	6	69828	10001	30006	10	10	0	10000	40010	70061	70042	70061	70061	70061
50024	70060	525	1	1	0	1	0	0	2	0	0	0	70045	69725	59717	25	40018	30016	10001	30010	10000	615508	3342542	49	66980	70060	70060	63409	3	63742	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10002	0	0	2	4	10000	0	1	1	1	0	0	2520	6	64	0	7	6	69820	10001	30006	13	0	13	10000	40010	70061	70061	70042	70061	70061
50024	70060	525	1	0	0	1	0	0	2	1	0	0	70045	69725	59713	25	40018	30016	10001	30010	10000	615508	3341614	49	66961	70060	70060	63428	3	63742	40010	30020	20000	60020	10000	70041	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10003	0	0	3	4	10000	1	1	1	1	1	0	2520	4	64	0	10	6	69809	10001	30006	0	10	0	10000	40010	70061	70061	70042	70061	70058
50024	70060	525	1	1	0	0	0	0	2	0	0	0	70045	69725	59710	25	40014	30013	10001	30010	10000	615535	3341614	49	66961	70173	70061	63413	3	63722	40010	30020	20000	60020	10000	70060	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	0	10002	0	0	1	1	10000	1	1	1	1	0	0	2520	4	65	0	7	4	69807	10001	30003	13	10	13	10000	40010	70061	70061	70042	70061	70058
50024	70060	525	1	0	0	1	0	0	2	1	0	1	70026	69722	59710	25	40014	30013	10002	30010	10000	615535	3342542	49	66980	70041	70060	63428	3	63722	40010	30020	20000	60020	10000	70057	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	2	4	10000	1	1	0	1	0	0	2520	4	64	0	7	6	69807	10001	30006	13	10	0	10000	40010	70058	70061	70061	70058	70061
50024	70060	524	1	1	0	1	0	0	2	0	0	0	70026	69725	59710	25	40018	30016	10001	30010	10000	615535	3342542	49	66980	70060	70060	63409	3	63722	40010	30020	20000	60020	10000	70060	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	0	4	10000	1	1	1	1	1	0	2520	5	64	0	7	4	69822	10001	30006	13	0	0	10000	40010	70058	70042	70042	70061	70058
50024	70060	524	1	1	1	1	1	1	1	0	0	0	70045	69697	59710	25	40018	30016	10002	30010	10000	615508	3342542	49	66977	70060	70041	63428	3	63742	40010	30020	20000	60020	10000	70041	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10002	0	1	1	4	10000	0	1	0	1	2	0	2520	3	65	0	8	4	69824	10001	30006	13	13	0	10000	40010	70061	70058	70058	70042	70061
50024	70041	524	1	1	1	1	0	0	2	0	0	0	70042	69725	59713	25	40018	30013	10002	30010	10000	615508	3341614	49	66961	70041	70041	63409	3	63722	40010	30020	20000	60020	10066	70060	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	0	1	1	10000	1	1	1	1	1	0	2520	5	64	0	8	4	69822	10001	30006	13	13	13	10000	40010	70058	70042	70058	70061	70042
50024	70041	524	1	1	1	1	0	0	1	0	0	0	70045	69697	59713	25	40018	30016	10002	30010	10000	615508	3342542	49	66980	70060	70060	63428	3	63742	40010	30020	20000	60020	10000	70060	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	0	1	1	10000	1	1	0	1	1	0	2520	4	64	0	7	3	69821	10001	30006	13	0	13	10000	40010	70058	70061	70042	70042	70061
50024	70041	525	1	1	1	1	0	1	2	0	0	0	70042	69697	59710	25	40014	30016	10002	30010	10000	615535	3341614	49	66980	70057	70041	63409	3	63722	40010	30020	20000	60020	10000	70041	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	0	1	1	10000	1	1	1	1	1	0	2520	4	64	0	10	6	69858	10001	30006	13	10	13	10000	40010	70061	70061	70061	70058	70042

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldnp x0, x1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70047	524	0	0	0	0	1	1	0	0	432	0	1	0	0	70020	69711	59723	25	40104	30103	10002	30111	10007	613465	3341473	1	49	66955	70035	70047	63440	8	63746	40118	30233	20023	60266	10012	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	1	1	1	2621	0	16	0	0	69845	10000	30003	0	6	0	10000	40100	70036	70051	70051	70051	70051
50204	70050	525	0	0	0	0	1	0	0	0	6	0	0	0	0	70020	69711	59733	25	40104	30100	10000	30111	10007	613202	3342075	1	49	66970	70035	70035	63509	8	63730	40118	30233	20023	60266	10012	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	0	0	0	0	0	1	1	1	2621	0	16	0	0	69861	10000	30003	9	6	9	10000	40100	70051	70051	70036	70036	70051
50204	70050	524	0	0	0	0	0	0	0	0	70	0	0	0	0	70020	69714	59724	25	40100	30100	10001	30111	10007	613202	3341473	1	49	66970	70051	70050	63491	7	63731	40118	30233	20023	60266	10012	70050	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	1	1	1	2620	0	16	0	0	70192	10000	30003	0	6	0	10000	40100	70484	70332	70369	70276	70048
50204	70050	525	0	0	1	0	0	1	3	0	14	790	1	0	0	70035	69714	59733	25	40100	30103	10006	30250	10000	613915	3342056	1	49	66970	70035	70047	63462	3	63710	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	0	0	2610	1	64	1	1	69813	10000	30003	0	0	9	10000	40100	70036	70053	70051	70036	70042
50204	70035	525	0	0	0	0	0	0	0	0	7	0	0	0	0	70035	69714	59684	25	40104	30103	10001	30100	10000	613915	3342056	1	49	66970	70050	70050	63447	3	63707	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	45	10000	1	0	1	0	0	0	0	0	0	2610	1	64	1	1	69798	10000	30000	0	0	9	10000	40100	70036	70036	70051	70051	70039
50204	70050	524	0	0	0	0	0	0	0	0	31	0	0	0	0	70020	69721	59700	25	40104	30100	10001	30100	10000	613756	3342056	1	49	63993	70051	70117	63404	3	63719	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	0	0	0	0	0	0	0	2610	1	64	1	1	69813	10000	30003	0	6	9	10000	40100	70036	70036	70036	70051	70051
50204	70035	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70020	69711	59694	25	40104	30103	10001	30100	10000	613915	3342056	1	49	66970	70047	70050	63491	3	63707	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	0	0	0	2610	1	64	1	1	69813	10000	30003	9	0	6	10000	40100	70052	70036	70051	70051	70051
50204	70050	524	0	0	0	0	0	0	0	0	0	0	1	0	0	70035	69714	59700	25	40104	30100	10001	30100	10000	613652	3342056	1	49	66955	70047	70047	63447	3	63695	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	0	0	2	2610	1	64	1	1	69813	10000	30000	0	6	0	10000	40100	70036	70051	70051	70051	70048
50204	70047	525	0	0	0	0	0	0	0	0	1	0	1	0	0	70035	69698	59700	25	40104	30100	10000	30100	10000	613915	3341304	1	49	66976	70035	70047	63422	3	63710	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	0	0	0	0	0	2610	1	64	1	1	69813	10001	30000	9	9	0	10000	40100	70048	70042	70057	70057	70036
50204	70050	524	0	0	0	0	0	0	0	0	1	0	0	0	0	70020	69714	59700	25	40104	30100	10000	30100	10000	613915	3342056	1	49	66955	70047	70047	63431	3	63713	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	0	0	0	0	0	0	0	0	2610	1	64	1	1	69813	10000	30003	0	0	9	10000	40100	70051	70051	70036	70051	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ld nt uop (e6)	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70047	525	0	0	1	0	1	1	1	0	0	1	0	0	0	0	70035	69714	59689	25	40014	30010	10001	30010	10000	615102	3341899	0	0	49	66971	70047	70056	63403	3	63718	40010	30020	20000	60020	10000	70054	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	5	0	0	10000	1	1	0	0	2520	0	6	78	0	0	0	13	12	69802	10000	30000	9	6	6	10000	40010	70051	70048	70052	70057	70051
50024	70050	525	0	0	0	0	0	0	0	0	0	1	0	0	0	0	70209	69714	59677	25	40014	30010	10000	30584	10000	616899	3341899	1	1	49	66994	70321	70056	63408	3	63715	40010	30660	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	4	2	0	10000	1	1	2	0	2520	0	11	78	1	0	1	12	13	69814	10000	30003	9	24	6	10000	40010	70048	70051	70048	70048	70051
50024	70047	525	0	0	0	0	0	1	0	0	0	0	0	1	0	0	70032	69714	59689	25	40014	30013	10001	30010	10000	615126	3341295	0	0	49	67034	70035	70035	63415	3	63682	40010	30344	20110	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	0	0	2520	0	11	78	0	0	0	12	11	69817	10000	30000	9	6	0	10000	40010	70036	70051	70090	70048	70036
50024	70056	525	0	0	0	0	0	0	0	0	0	1	0	1	0	0	70032	69719	59694	25	40014	30010	10000	30010	10000	615102	3341295	0	1	49	67006	70050	70055	63418	3	63682	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	2520	0	14	78	0	0	0	12	13	69801	10000	30003	0	6	0	10000	40010	70036	70036	70036	70036	70051
50024	70327	525	0	0	0	0	0	0	0	0	0	1	0	0	0	0	70032	69714	59677	25	40014	30013	10001	30296	10000	615207	3341295	0	1	49	67018	70038	70049	63415	3	63718	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	2520	0	12	78	0	0	0	12	12	69801	10000	30003	9	6	6	10000	40010	70036	70039	70048	70036	70036
50024	70035	524	0	0	0	0	0	0	0	0	0	0	0	1	0	0	70035	69719	59692	25	40014	30013	10001	30010	10000	615126	3341295	0	0	49	66996	70048	70047	63403	3	63715	40010	30020	20000	60020	10000	70047	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	2520	0	13	78	0	0	0	13	13	69817	10000	30003	6	0	6	10000	40010	70036	70036	70051	70036	70036
50024	70050	524	0	0	0	0	0	0	0	0	0	0	0	1	0	0	70032	69718	59689	25	40014	30013	10001	30010	10000	614994	3342046	0	0	49	67327	70086	70038	63418	3	63718	40010	30020	20000	60020	10000	70047	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	2520	0	13	78	0	0	0	13	13	69801	10000	30003	0	6	6	10000	40010	70036	70048	70048	70051	70051
50024	70047	525	0	0	0	0	0	0	0	0	0	1	0	1	0	0	70020	69714	59689	25	40014	30013	10001	30010	10000	615129	3346737	0	0	49	67017	70053	70048	63418	3	63682	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	0	1	0	0	2520	0	14	99	0	0	0	13	13	69814	10000	30000	9	0	6	10000	40010	70036	70048	70048	70051	70048
50024	70047	524	0	0	0	0	0	0	0	0	0	1	0	0	0	0	70032	69714	59692	25	40014	30013	10000	30010	10000	614994	3342046	0	1	49	66967	70051	70035	63415	3	63682	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	3	0	0	10000	1	1	0	0	2520	0	13	78	1	0	0	13	5	69814	10000	30000	6	18	18	10000	40010	70048	70036	70036	70036	70048
50024	70050	525	0	0	0	0	0	1	0	0	0	1	0	0	0	0	70020	69714	59692	25	40010	30013	10000	30010	10000	615021	3341295	0	0	49	67050	70052	70047	63418	3	63718	40010	30020	20000	60020	10000	70056	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	3	10000	0	0	0	0	2520	0	12	99	0	0	0	13	13	69817	10000	30003	0	6	9	10000	40010	70051	70051	70036	70048	70051

Test 4: throughput

Count: 8

Code:

  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]
  ldnp x0, x1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26728	200	0	0	141	1	0	26712	0	1	1	0	25	80100	100	80000	100	80000	500	1168880	49	23629	26727	26717	6667	0	3	6685	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	1	100	80000	43	0	80039	0	42	80038	6	1	39	43	5110	1	16	0	1	4	26724	80000	10	10	7	80000	80100	26732	26732	26732	26732	26732
160204	26731	201	0	0	44	0	0	26716	0	12	1	0	25	80100	100	80000	100	80000	500	1168778	49	23750	26737	26727	6657	0	3	6689	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80038	0	39	80000	6	1	39	0	5110	3	16	0	2	4	26728	80000	14	0	7	80000	80100	26732	26708	26728	26732	26732
160204	26731	200	0	0	44	0	1	26692	2	1	0	19	25	80100	100	80000	100	80000	500	1168627	49	23737	26707	27209	6630	0	3	6691	80100	200	160000	200	80000	26739	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80038	0	0	80038	6	0	0	0	5110	3	16	0	4	3	26724	80038	0	10	0	80000	80100	26728	26711	26732	26732	26728
160204	26707	200	0	0	0	0	1	26716	2	1	12	19	25	80100	100	80000	100	80000	500	1168880	49	23749	26876	26714	6654	0	3	6685	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80000	0	0	80038	6	0	39	44	5110	4	16	0	3	2	26728	80038	14	10	0	80000	80100	26732	26708	26728	26732	26708
160204	26707	199	0	0	0	1	1	26716	2	0	1	19	25	80100	100	80000	100	80000	500	1174887	49	23753	26737	26717	6664	0	3	6689	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80038	0	39	80038	0	1	39	44	5110	3	16	0	3	2	26728	80038	10	10	7	80000	80100	26732	26732	26708	26732	26708
160204	26731	200	0	0	45	1	1	26712	0	1	0	19	25	80100	100	80000	100	80000	500	1168880	49	23781	26737	26736	6663	0	3	6689	80100	200	160000	200	80000	26707	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80038	0	39	80038	0	1	39	43	5110	3	16	0	2	2	26728	80038	14	10	7	80000	80100	26732	26708	26708	26708	26708
160204	26731	200	0	0	44	0	1	26716	2	1	1	19	25	80100	100	80000	100	80000	500	1168880	49	23766	26737	26735	6674	0	3	6689	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80038	0	39	80000	6	0	0	44	5110	3	16	0	3	1	26704	80038	0	0	7	80000	80100	26732	26728	26732	26735	26728
160204	26731	200	0	0	44	0	1	26716	2	1	12	16	25	80100	100	80000	100	80000	500	1168880	49	23663	26707	26745	6662	0	3	6667	80100	200	160000	200	80000	26733	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80000	0	38	80039	6	1	39	44	5110	1	16	0	1	3	26728	80039	14	10	0	80000	80100	26732	26732	26728	26708	26732
160204	26731	200	0	0	105	0	1	26720	3	0	1	0	25	80100	100	80000	100	80000	500	1174887	49	23647	26733	26749	6654	0	3	6691	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80038	0	38	80000	6	0	0	43	5110	3	16	0	5	2	26728	80038	10	10	0	80000	80100	26732	26708	26732	26732	26728
160204	26707	200	0	0	44	0	0	26712	2	0	1	19	25	80100	100	80000	100	80000	500	1168880	49	23760	26737	26736	6668	0	3	6689	80100	200	160000	200	80000	26731	35	1	1	80201	100	99	100	80000	100	80000	0	100	80000	43	0	80000	0	38	80038	6	1	39	44	5110	1	16	0	2	3	26728	80038	0	10	7	80000	80100	26732	26708	26732	26732	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3348

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ld nt uop (e6)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26729	200	1	0	0	0	1	0	1	26692	0	0	0	0	25	80010	10	80000	10	80000	50	1168058	49	23651	26707	26731	6653	0	3	6687	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	1	38	80039	6	0	39	44	0	0	5020	0	1	16	1	1	26728	80038	14	0	4	80000	80010	26728	26732	26708	26732	26732
160024	26731	200	0	0	0	0	0	0	0	26712	2	0	0	0	25	80010	10	80000	10	80000	50	1172556	49	23651	26727	26731	6672	0	3	6687	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80038	6	1	0	44	0	0	5020	0	1	16	1	1	26728	80038	14	14	7	80000	80010	26732	26708	26732	26708	26708
160024	26731	200	0	0	0	0	0	0	1	26716	0	1	1	19	25	80010	10	80000	10	80000	50	1177654	49	23651	26707	26707	6672	0	3	6687	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	0	80039	6	1	39	44	0	0	5020	0	1	16	1	1	26728	80038	0	14	0	80000	80010	26732	26732	26708	26732	26708
160024	26707	200	0	0	0	45	1	0	1	26716	2	1	0	19	25	80010	10	80000	10	80000	50	1168880	49	23651	26731	26731	6676	0	3	6707	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	1	0	80036	6	0	39	44	0	0	5020	0	1	16	1	1	26728	80039	14	0	7	80000	80010	26732	26732	26732	26732	26728
160024	26707	200	0	0	0	45	0	0	0	26692	2	1	0	19	25	80010	10	80000	10	80000	50	1175637	49	23627	26731	26731	6677	0	3	6687	80010	20	160000	20	80000	26727	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	0	80032	6	1	39	44	0	0	5020	0	1	16	1	1	26704	80000	14	7	7	80000	80010	26732	26732	26708	26732	26732
160024	26727	201	0	0	0	0	1	0	1	26692	2	1	0	0	25	80010	10	80000	10	80000	50	1174628	49	23651	26731	26731	6676	0	3	6711	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	0	80038	0	0	39	0	0	0	5020	0	1	16	1	1	26729	80000	14	0	7	80000	80010	26732	26732	26708	26732	26735
160024	26731	200	0	0	0	44	1	0	1	26716	2	1	0	0	25	80010	10	80000	10	80000	50	1179233	49	23651	26731	26731	6676	0	3	6711	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80039	6	0	39	44	0	0	5020	0	1	16	1	1	26728	80038	0	10	7	80000	80010	26732	26728	26708	26732	26728
160024	26707	200	0	1	0	44	0	0	1	26716	0	0	1	0	25	80010	10	80000	10	80000	50	1177236	49	23627	26731	26731	6677	0	3	6707	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80038	6	1	39	0	0	0	5020	0	1	16	1	1	26728	80038	0	0	7	80000	80010	26732	26732	26732	26732	26708
160024	26707	200	0	0	0	44	0	0	1	26692	0	1	1	16	25	80010	10	80000	10	80000	50	1168500	49	23651	26727	26727	6676	0	3	6711	80010	20	160000	20	80000	26733	35	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	80168	0	38	80039	6	1	0	0	0	0	5020	0	1	16	1	1	26728	80169	0	0	7	80000	80010	26732	26708	26732	26728	26708
160024	26707	200	0	0	0	44	0	0	0	26692	0	0	0	0	25	80010	10	80000	10	80000	50	1173947	49	23651	26731	26731	6677	0	3	6711	80010	20	160000	20	80000	26731	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	41	80000	6	0	39	0	1	0	5020	0	1	16	1	1	26825	80039	0	14	7	80000	80010	26732	26732	26708	26732	26732

LDNP (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations