Firestorm: LDRH (post-index) measurements

Code:

  ldrh w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	8	0	0	0	104	0	0	0	6	0	1025	10	8	5	8	31	25	2000	1000	1000	1000	1000	52828	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1019	1	79	1033	0	0	0	0	27	1023	53	8	30	64	0	73	1	16	1	1	1037	1000	28	25	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	75	0	0	0	1	0	1025	0	1	3	7	20	25	2000	1000	1000	1000	1000	52824	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1013	0	57	1027	0	0	0	0	31	1037	39	6	23	56	0	73	1	16	1	1	1037	1000	19	27	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	69	0	0	0	1	0	1025	10	1	5	17	21	25	2000	1000	1000	1000	1000	52824	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1013	1	78	1058	4	2	23	8	39	1036	57	8	35	64	0	73	1	16	1	1	1037	1000	26	17	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	60	13	0	0	2	4	1025	13	8	8	9	27	25	2000	1000	1000	1000	1000	52836	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1017	0	66	1037	9	0	12	0	35	1023	38	8	25	48	0	73	1	16	1	1	1037	1000	21	27	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	112	19	1	0	4	0	1025	15	5	3	46	29	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1019	1	94	1049	5	2	19	12	69	1048	41	6	29	64	0	73	1	16	1	1	1037	1000	28	24	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	97	17	1	0	5	0	1025	0	6	6	7	17	25	2000	1000	1000	1000	1000	52824	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1016	0	65	1043	5	1	16	12	38	1025	45	7	27	64	0	73	1	16	1	1	1037	1000	26	23	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	0	64	0	1	0	3	0	1025	17	11	10	9	27	25	2000	1000	1000	1000	1000	52824	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1000	0	61	1032	0	1	0	0	31	1023	43	6	21	56	0	73	1	16	1	1	1037	1000	30	22	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	0	63	21	0	0	2	4	1025	0	1	3	8	21	25	2000	1000	1000	1000	1000	52816	45822	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1013	0	73	1075	2	1	38	18	31	1063	48	9	30	58	0	73	1	16	1	1	1037	1000	28	27	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	1	0	68	19	1	8	2	0	1025	15	2	4	15	20	25	2000	1000	1000	1000	1000	52828	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1017	1	68	1042	11	0	19	10	40	1057	39	8	40	64	1	73	1	16	1	1	1037	1000	23	27	1000	1000	1041	1041	1045	1041	1041
2004	1040	8	0	0	0	63	0	0	0	3	12	1025	19	5	3	6	21	25	2000	1000	1000	1000	1000	52824	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1017	1	80	1044	1	0	16	18	28	1033	39	8	23	56	0	73	1	16	1	1	1037	1000	30	27	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1876

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	18	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72332	540	2	0	1	0	0	446	0	797	1	712	1	112	71902	820	0	3	71668	25	50775	40608	10110	40100	10000	614505	2732910	0	49	68754	71989	71805	65270	3	65636	50100	40200	10000	70200	10000	71876	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10915	2	149	476	10633	275	12	929	48	20	10990	113	1	134	1	0	3	0	2610	2	58	1	1	71805	40500	1107	1156	1094	10000	40100	71891	71988	72019	72043	71945
50204	71829	540	3	1	0	0	0	446	0	784	1	704	1	136	71866	802	0	3	71763	25	50695	40616	10132	40100	10000	613732	2726156	1	49	68809	71826	71907	65203	3	65479	50100	40200	10000	70200	10000	72040	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10902	1	144	468	10625	248	11	906	74	29	10954	123	1	123	1	0	6	0	2610	1	58	1	1	71708	40492	1020	1090	1103	10000	40100	71876	71898	71994	71958	71876
50204	71858	538	2	0	0	0	0	480	0	807	1	696	2	112	72045	803	2	1	71372	25	50765	40620	10124	40100	10000	613941	2736571	1	49	68856	71974	71893	65241	3	65510	50100	40200	10000	70200	10000	72020	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10921	2	149	466	10620	267	12	870	48	22	10999	123	3	129	1	0	5	0	2610	1	50	1	1	71567	40496	1131	1105	1116	10000	40100	72080	71995	71882	71859	71884
50204	71959	538	1	1	0	0	0	481	0	774	1	720	1	132	71959	784	1	0	71592	25	50735	40592	10119	40100	10041	614632	2732003	1	49	68743	71963	72034	65363	3	65683	50100	40200	10000	70200	10000	71853	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10912	1	155	483	10623	249	9	906	48	33	11012	117	1	122	1	0	10	0	2610	1	58	1	1	71799	40504	1048	1034	1061	10000	40100	71861	71768	72029	71853	71942
50204	71702	537	1	0	0	0	0	434	0	835	1	728	1	132	71835	798	1	0	71676	25	50715	40584	10131	40100	10000	615019	2732433	1	49	68805	71922	71927	65392	3	65494	50100	40200	10000	70200	10000	72062	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10915	1	174	507	10653	257	12	889	46	29	10974	135	2	135	1	0	6	0	2610	1	58	1	1	71493	40488	1014	1059	1016	10000	40100	71804	72065	72045	71992	72105
50204	71890	538	2	0	0	0	0	459	0	816	1	712	1	140	71975	796	1	0	71568	25	50730	40668	10115	40100	10000	615357	2722804	1	49	68916	71768	71853	65300	3	65591	50100	40200	10000	70200	10000	71971	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10882	1	140	492	10646	262	13	880	86	25	10983	126	3	121	1	3	9	0	2610	1	58	1	1	71751	40472	1110	1134	1138	10000	40100	72003	71808	71929	72094	71965
50204	72066	539	2	0	1	0	0	475	0	900	1	672	2	140	72043	762	1	0	71601	25	50790	40612	10133	40100	10000	614831	2734150	1	49	68970	72073	71799	65237	3	65553	50100	40200	10000	70200	10000	72109	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10878	1	159	475	10647	262	8	897	48	17	10976	133	2	130	1	0	5	0	2641	1	58	1	1	71782	40516	1028	1001	1068	10000	40100	71856	72070	71820	71752	71972
50204	72067	538	2	0	1	0	0	472	0	812	1	696	1	116	71866	787	1	2	71511	25	50755	40608	10123	40100	10000	614791	2715539	1	49	68876	71913	71830	65308	3	65738	50100	40200	10000	70200	10000	71961	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10899	1	163	504	10646	264	12	904	28	35	10960	121	3	126	1	0	6	0	2610	1	58	1	1	71815	40560	1022	1180	1070	10000	40100	71983	71800	71916	72105	72058
50204	71934	540	1	0	0	0	0	431	0	817	1	680	1	112	71659	780	0	0	71652	25	50640	40612	10133	40100	10000	614634	2726320	0	49	68764	71854	72191	65268	3	65452	50100	40200	10000	70200	10000	71801	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10913	1	163	501	10638	271	12	884	48	20	10941	133	1	119	1	2	7	0	2610	1	58	1	1	71750	40524	1117	1031	1089	10000	40100	71837	71940	71954	71945	72003
50204	71732	539	1	0	0	0	0	461	0	796	1	696	1	128	71894	773	1	0	71495	25	50740	40620	10118	40100	10000	614475	2730172	1	49	68759	71736	71968	65438	3	65596	50100	40200	10000	70200	10000	71982	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10875	1	160	496	10617	269	11	886	46	32	10948	126	3	126	1	0	5	0	2610	1	58	1	1	71712	40520	998	1110	1122	10000	40100	71847	71670	71725	71946	71891

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1952

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72349	539	3	0	0	0	0	0	0	0	458	340	854	1	744	5	120	71811	840	6	2	71721	25	50706	40527	10146	40010	10000	612704	2732047	0	49	68969	71859	71955	65639	3	65681	50010	40020	10000	70020	10000	72194	35	1	1	40021	10	9	10	10000	30010	10000	10	10956	23	140	542	10670	254	13	962	70	41	10973	130	3	124	1	0	7	0	0	2520	1	9	85	7	11	71834	40540	1191	1210	1115	10000	40010	72057	72085	71986	72037	71863
50024	71949	539	2	0	0	0	0	0	0	0	432	0	852	1	720	4	156	72076	800	2	2	71839	25	50695	40554	10143	40010	10000	613135	2732822	0	49	68774	71968	71820	65707	3	65677	50010	40020	10000	70020	10000	72163	35	1	1	40021	10	9	10	10000	30010	10000	10	10933	11	176	518	10686	282	13	967	78	32	10953	132	5	137	1	3	17	0	0	2520	0	8	85	6	11	71900	40528	1127	1196	1108	10000	40010	72133	71946	72128	71871	71966
50024	71897	540	3	0	0	0	0	0	0	0	422	0	820	1	744	1	116	71808	796	0	2	71580	25	50630	40526	10141	40010	10000	612226	2726026	1	49	68896	71989	71753	65322	3	65547	50010	40020	10000	70020	10000	72086	35	1	1	40021	10	9	10	10000	30010	10000	10	10907	2	186	502	10634	274	8	931	84	16	10925	117	4	134	2	7	3	0	0	2520	0	6	85	6	7	71522	40472	1040	952	1167	10000	40010	72006	71951	71969	71989	72114
50024	72021	538	3	3	0	3	0	0	0	0	515	0	848	1	696	3	140	72173	799	1	3	71647	25	50690	40590	10145	40010	10000	612810	2727480	0	49	68772	72054	71730	65384	3	65649	50010	40020	10000	70020	10051	71996	35	1	1	40021	10	9	10	10000	30010	10000	10	10913	10	144	521	10659	269	12	945	80	38	10935	124	6	131	1	2	3	0	0	2520	0	8	85	6	7	71811	40528	1069	1030	995	10000	40010	71902	72164	72109	72005	71920
50024	72213	539	2	0	0	0	0	0	0	0	412	0	838	1	736	3	124	71867	805	3	2	71882	25	50660	40518	10138	40010	10000	613455	2731402	0	49	68893	71873	72136	65480	3	65758	50010	40020	10000	70020	10000	72085	35	1	1	40021	10	9	10	10000	30010	10000	10	10946	12	130	489	10659	287	14	950	72	29	10938	142	9	132	1	3	4	0	0	2520	0	7	85	10	6	71868	40584	1086	1197	1179	10000	40010	71866	71893	71899	71893	72095
50024	72088	540	2	0	0	0	0	0	0	0	571	0	862	1	736	4	76	71927	819	3	8	71574	25	50660	40514	10125	40010	10000	612634	2720300	0	49	68637	71690	71962	65714	3	65798	50010	40020	10000	70020	10000	72067	35	2	1	40021	10	9	10	10000	30010	10000	10	10928	23	153	486	10672	278	10	959	36	34	10951	125	2	127	2	7	3	0	0	2520	0	7	85	11	6	71983	40556	1076	1063	1180	10000	40010	72085	71982	71994	71892	71866
50024	71625	539	3	0	0	0	0	0	0	0	416	0	874	1	800	3	116	72108	810	6	2	71744	25	50685	40514	10139	40010	10000	615992	2732368	1	49	68765	71979	71963	65636	3	65695	50010	40020	10000	70020	10000	71872	35	1	1	40021	10	9	10	10000	30010	10000	10	10904	16	148	507	10642	274	8	945	86	22	10949	131	5	137	2	0	3	0	0	2520	0	7	85	8	13	71914	40544	1071	1078	1145	10000	40010	71984	71951	71835	71882	71955
50024	71924	539	2	2	2	0	0	0	0	0	421	0	822	1	688	5	120	71923	831	2	2	71670	25	50665	40538	10144	40010	10000	613610	2729000	0	49	68934	71994	71843	65427	3	65718	50010	40020	10000	70020	10000	71971	35	1	1	40021	10	9	10	10000	30010	10000	10	10929	16	143	491	10667	262	13	941	74	23	10945	131	3	131	0	3	5	0	0	2520	0	7	85	8	5	71771	40560	1159	1128	1126	10000	40010	71813	71980	71714	71940	71913
50024	71940	539	2	0	0	0	0	0	0	0	459	0	836	1	728	5	120	72011	834	3	2	71750	25	50660	40554	10135	40010	10000	613693	2727911	1	49	68783	71867	72137	65567	3	65704	50010	40020	10000	70020	10000	71965	35	1	1	40021	10	9	10	10000	30010	10000	10	10926	25	136	515	10678	281	11	964	48	27	10945	122	4	129	2	1	3	0	0	2520	0	7	85	11	7	71831	40540	1065	1112	1162	10000	40010	71965	72032	71988	71938	72046
50024	71970	539	4	1	0	4	0	0	0	0	452	0	847	1	720	4	280	71935	825	3	2	71745	25	50680	40530	10131	40010	10000	614413	2729273	0	49	68813	71966	71985	65691	3	65546	50010	40020	10000	70020	10000	72196	35	1	1	40021	10	9	10	10000	30010	10000	10	10973	17	150	494	10677	269	11	967	78	27	10956	139	5	129	1	0	7	0	0	2520	0	6	85	5	8	71845	40548	1062	1091	1099	10000	40010	71914	71952	71835	71938	71884

Test 3: throughput

Count: 8

Code:

  ldrh w0, [x6], #8
  ldrh w0, [x7], #8
  ldrh w0, [x8], #8
  ldrh w0, [x9], #8
  ldrh w0, [x10], #8
  ldrh w0, [x11], #8
  ldrh w0, [x12], #8
  ldrh w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3691

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	30057	221	2	0	1	0	0	7141	804	1	792	112	104	29591	823	805	1588	1904	2265	25	160155	80160	80000	80100	80000	400815	1307370	1	68	49	26376	29537	29548	9412	0	3	9422	160100	80200	80000	80200	80000	29592	35	1	1	80201	100	99	35	100	80000	100	80000	1	100	80948	37	393	5529	0	85260	681	12	914	50	5529	85748	831	125	5618	5189	18	1	3	5110	1	16	1	1	29509	26	80066	560	686	117	80000	80100	29496	29431	29528	29451	29508
160204	29276	219	2	0	0	0	0	7281	825	1	736	118	120	29589	807	768	1547	1710	2121	25	160162	80150	80000	80100	80000	400778	1290544	0	60	49	26391	29612	29635	9302	0	3	9464	160100	80200	80000	80200	80000	29431	35	1	1	80201	100	99	34	100	80000	100	80000	0	100	80909	17	396	5396	0	85818	637	14	906	80	5491	86446	705	124	5243	5129	16	0	3	5110	1	16	1	1	29474	38	80071	654	602	122	80000	80100	29662	29520	29499	29503	29406
160204	29533	220	1	0	0	0	0	7020	846	1	728	114	136	29453	816	674	1430	1965	2082	25	160167	80152	80000	80100	80000	400806	1305237	0	46	49	26348	29435	29521	9341	0	3	9393	160100	80200	80000	80200	80000	29379	35	1	1	80201	100	99	42	100	80000	100	80000	1	100	80912	16	411	5554	0	85157	655	16	928	72	4967	86285	771	123	5034	4947	15	6	3	5110	1	16	1	1	29552	20	80052	650	648	101	80000	80100	29514	29526	29331	29515	29770
160204	29329	220	1	0	0	0	0	7177	829	1	696	89	132	29393	791	757	1614	1668	2181	25	160157	80170	80000	80100	80000	400795	1297506	0	61	49	26220	29745	29499	9548	0	3	9561	160100	80200	80000	80200	80000	29523	35	1	1	80201	100	99	50	100	80000	100	80000	0	100	80910	17	379	5200	0	85448	666	11	921	80	4621	86627	820	127	4760	5117	13	3	4	5110	1	16	1	1	29470	29	80076	587	590	114	80000	80100	29698	29375	29576	29566	29441
160204	29626	222	1	0	0	0	0	6568	817	1	696	101	108	29359	805	681	1785	1775	2239	25	160158	80171	80000	80100	80000	400876	1298752	0	56	49	26501	29500	29365	9347	0	3	9355	160100	80200	80000	80200	80000	29312	35	1	1	80201	100	99	49	100	80000	100	80000	0	100	80924	0	373	5504	0	84752	659	11	928	74	5111	85950	758	136	5222	4773	0	0	11	5110	1	16	1	1	29377	22	80059	680	633	125	80000	80100	29431	29497	29516	29645	29545
160204	29401	221	0	0	0	0	0	6994	837	1	720	113	192	29472	787	651	1449	1863	2045	25	160169	80172	80000	80100	80000	400794	1305931	0	58	49	26471	29543	29411	9564	0	3	9455	160100	80200	80000	80200	80000	29513	35	1	1	80201	100	99	32	100	80000	100	80000	0	100	80922	17	412	5288	0	85469	674	15	919	38	5024	86010	766	125	5208	5115	15	0	3	5110	1	16	1	1	29525	34	80064	658	654	123	80000	80100	29542	29572	29501	29396	29519
160204	29593	220	1	0	0	0	0	6727	827	1	776	121	152	29456	824	701	1784	1856	2097	25	160166	80156	80000	80100	80000	400776	1307413	0	63	49	26362	29368	29337	9439	0	3	9466	160100	80200	80000	80200	80000	29427	35	1	1	80201	100	99	42	100	80000	100	80000	0	100	80893	16	403	5506	0	85103	644	12	909	34	4926	86430	686	127	5442	5834	16	0	5	5110	1	17	1	1	29544	31	80056	685	647	102	80000	80100	29574	29427	29495	29379	29570
160204	29558	221	3	3	0	0	0	7218	824	1	704	102	116	29420	797	761	1663	1733	2471	25	160161	80162	80000	80100	80000	400790	1294207	0	60	49	26403	29569	29583	9286	0	3	9384	160100	80200	80000	80200	80000	29596	35	1	1	80201	100	99	45	100	80000	100	80000	0	100	80929	34	338	5625	0	85384	627	11	927	70	5537	86028	675	114	5212	5345	33	0	3	5110	1	16	1	1	29590	38	80052	670	616	93	80000	80100	29600	29505	29522	29552	29594
160204	29399	220	2	0	2	0	0	6611	822	1	680	118	160	29651	818	730	1573	1916	2129	25	160168	80167	80000	80100	80000	400804	1305739	0	65	49	26535	29466	29569	9273	0	3	9557	160100	80200	80000	80200	80000	29394	35	1	1	80201	100	99	41	100	80000	100	80000	0	100	80970	19	428	5209	0	85140	661	12	914	80	5337	86033	754	126	5206	5661	0	24	4	5110	1	16	1	1	29546	28	80056	619	595	112	80000	80100	29459	29617	29595	29449	29575
160204	29511	222	1	0	0	0	0	6663	830	1	536	125	136	29584	794	804	1936	2189	2182	25	160158	80172	80000	80100	80000	400835	1297004	0	58	49	26568	29486	29415	9394	0	3	9399	160100	80200	80000	80200	80000	29562	35	1	1	80201	100	99	45	100	80000	100	80000	0	100	80918	18	418	5066	0	85037	676	15	882	130	4765	85887	685	131	4521	5323	13	0	0	5110	1	16	1	1	29375	33	80071	633	659	90	80000	80100	29531	29624	29654	29545	29475

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3681

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29923	220	2	0	1	1	0	0	0	7276	815	1	728	129	136	29489	802	360	1758	1876	2285	25	160074	80078	80000	80010	80000	400336	1300727	1	62	49	26383	29330	29618	9413	0	3	9301	160010	80020	80000	80020	80000	29331	35	1	1	80021	10	9	30	10	80000	10	80000	0	10	80947	37	380	5021	85448	654	7	888	44	5190	85741	764	132	5082	4632	50	0	3	5020	9	16	0	1	6	2	29503	31	80059	532	590	103	80000	80010	29494	29600	29382	29406	29438
160024	29433	220	2	0	0	0	0	0	0	6509	846	1	752	118	156	29280	809	363	1925	1938	2190	25	160075	80063	80000	80010	80000	400377	1306663	0	47	49	26461	29415	29568	9439	0	3	9449	160010	80020	80000	80020	80000	29475	35	1	1	80021	10	9	23	10	80000	10	80000	0	10	80957	38	404	5380	85308	722	23	941	76	4957	85704	808	147	5144	5574	36	3	0	5020	2	16	0	0	2	2	29568	33	80067	556	569	89	80000	80010	29431	29530	29328	29602	29479
160024	29334	220	2	0	2	0	1	0	0	6965	826	1	736	130	116	29367	832	413	1841	1642	2242	25	160059	80070	80000	80010	80000	400293	1293459	0	73	49	26360	29487	29628	9370	0	3	9425	160010	80020	80000	80020	80000	29452	35	1	1	80021	10	9	46	10	80000	10	80000	0	10	80950	36	371	5396	85567	681	8	948	70	4958	86263	846	132	4746	5176	37	0	118	5020	3	16	0	0	2	3	29402	24	80059	630	618	99	80000	80010	29404	29391	29400	29440	29223
160024	29560	222	2	0	0	0	0	0	0	6781	843	1	584	125	100	29577	820	395	1718	1795	2016	25	160069	80072	80000	80010	80000	400371	1301597	0	62	49	26415	29423	29406	9426	0	3	9375	160010	80020	80000	80020	80000	29482	35	1	1	80021	10	9	50	10	80000	10	80000	0	10	80954	36	357	5696	85551	644	11	944	78	5512	85868	797	126	5159	5866	37	0	3	5020	2	16	0	0	6	2	29489	35	80059	559	634	115	80000	80010	29475	29425	29373	29511	29383
160024	29330	219	2	0	2	0	0	0	0	7081	862	1	704	127	124	29264	824	397	1684	1703	2267	25	160087	80080	80000	80010	80000	400279	1298445	0	52	49	26456	29284	29327	9302	0	3	9385	160010	80020	80000	80020	80000	29343	35	1	1	80021	10	9	41	10	80000	10	80000	0	10	80975	37	401	5715	85347	649	10	956	48	5350	86170	842	142	5257	5615	36	0	3	5020	2	16	2	0	6	2	29416	33	80050	572	572	104	80000	80010	29559	29496	29404	29396	29363
160024	29554	221	2	0	1	0	1	0	0	6853	818	1	792	126	108	29300	810	382	1661	1839	2274	25	160068	80073	80000	80010	80000	400327	1304734	0	66	49	26315	29522	29608	9455	0	3	9307	160010	80020	80000	80020	80000	29552	35	1	1	80021	10	9	53	10	80000	10	80000	0	10	80950	34	359	5148	85208	656	10	926	74	5252	86244	796	133	4772	5177	36	3	3	5020	6	16	0	0	2	2	29426	33	80058	554	608	97	80000	80010	29521	29435	29409	29512	29432
160024	29513	220	2	0	0	1	0	0	0	6777	852	1	800	128	128	29414	812	377	1670	1693	2165	25	160068	80074	80000	80010	80000	400361	1293436	0	55	49	26443	29492	29460	9402	0	3	9373	160010	80020	80000	80020	80000	29461	35	1	1	80021	10	9	52	10	80000	10	80000	0	10	80973	38	384	5363	85547	677	9	921	66	5114	86084	752	133	4932	5123	37	0	3	5020	2	15	0	0	2	6	29435	30	80065	600	522	98	80000	80010	29400	29281	29469	29371	29387
160024	29456	220	2	1	1	1	2	0	0	6518	835	1	712	117	144	29372	831	393	1837	1708	2268	25	160068	80080	80000	80010	80000	400327	1295743	0	63	49	26361	29487	29376	9309	0	3	9461	160010	80020	80000	80020	80000	29462	35	1	1	80021	10	9	51	10	80000	10	80000	0	10	80958	37	363	5691	85265	647	8	915	44	4673	85921	793	138	5049	5214	37	3	4	5020	6	16	0	0	6	3	29392	40	80060	583	585	109	80000	80010	29518	29387	29526	29413	29369
160024	29442	220	2	0	1	1	0	1	0	6646	824	1	696	137	128	29439	834	371	1637	1970	2157	25	160072	80068	80000	80010	80000	400294	1299302	0	59	49	26312	29497	29373	9550	0	3	9466	160010	80020	80000	80020	80000	29334	35	1	1	80021	10	9	36	10	80000	10	80000	0	10	80973	34	404	5404	85726	664	8	928	78	5178	86176	772	132	5010	5428	37	0	9	5020	2	16	0	0	3	6	29469	31	80065	584	578	92	80000	80010	29304	29335	29511	29469	29352
160024	29413	220	2	0	0	1	0	0	0	6994	823	1	736	115	120	29457	808	379	1686	1719	2093	25	160075	80072	80000	80010	80000	400322	1300194	0	55	49	26191	29431	29441	9395	0	3	9435	160010	80020	80000	80020	80000	29403	35	1	1	80021	10	9	58	10	80000	10	80000	0	10	80960	37	388	5409	85206	660	14	948	74	4892	85646	783	134	5031	5332	36	0	4	5020	2	16	0	0	2	2	29379	22	80055	611	488	105	80000	80010	29553	29421	29420	29472	29357

LDRH (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations