Firestorm: NGCS (register, 32-bit) measurements

Code:

  ngcs w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	12	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	142	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	2	2	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  ngcs w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	3	710	2	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	255	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	12	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	154	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	4	27	6	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	6	27	5	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	5	27	6	6	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	187	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	6	27	4	4	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20214	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	6	27	5	6	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	107	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8780	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	2	640	6	27	6	6	9997	10000	10010	10036	10036	10036	10084	10036
10024	10035	75	0	0	103	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10082	40	1	1	10021	10	9	10	10010	10	0	0	0	640	6	27	6	5	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	4	27	5	6	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	9	346	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	6	27	5	6	9997	10000	10010	10036	10130	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	7	27	6	6	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Chain cycles: 1

Code:

  ngcs w0, w1
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	0	93	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	124	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	1	0	0	1310	1	28	1	1	19992	20100	10100	20036	20173	20036	20036	20036
20204	20035	150	0	0	0	0	0	124	19926	25	20200	20200	20200	1298912	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20098	150	0	0	0	0	0	82	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	57	0	0	145	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	126	19926	25	20200	20200	20200	1297650	0	49	17001	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	3	1	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	9	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	8	17508	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	0	0	82	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	3	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	124	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	2	4	0	0	0	0	1310	1	28	1	1	19992	20168	10100	20036	20036	20036	20036	20036
20204	20035	150	2	1	0	0	0	187	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	0	195	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	2	27	2	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	3	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	124	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	363	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20066	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	82	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	1	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036

Test 4: Latency 3->2

Chain cycles: 1

Code:

  ngcs w0, w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	149	1	0	166	19930	25	20100	20100	20112	1297233	1	49	16955	0	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	0	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	149	19930	25	20100	20100	20112	1297233	1	49	17001	0	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	1	1	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	0	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	0	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	0	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	1	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	0	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	82	19930	25	20100	20122	20112	1297233	0	49	16955	0	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	0	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	0	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	214	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20066	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	124	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1270	2	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 5: Latency 3->3

Code:

  ngcs w0, w1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	536	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6956	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	1	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	78	375	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	77	300	61	9918	25	10020	10020	10020	647296	0	49	6956	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	77	369	61	9918	25	10020	10020	10020	647296	0	49	6956	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	78	0	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	78	0	61	9918	25	10020	10020	10020	647296	0	49	6956	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	844	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	0	49	6956	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	664	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	604	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	42	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	640	3	27	2	2	10024	10010	10010	10036	10036	10036	10036	10036

Test 6: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ngcs w0, w8
  ands xzr, xzr, xzr
  ngcs w1, w8
  ands xzr, xzr, xzr
  ngcs w2, w8
  ands xzr, xzr, xzr
  ngcs w3, w8
  ands xzr, xzr, xzr
  ngcs w4, w8
  ands xzr, xzr, xzr
  ngcs w5, w8
  ands xzr, xzr, xzr
  ngcs w6, w8
  ands xzr, xzr, xzr
  ngcs w7, w8

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
160204	53409	400	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	0	6	19	6	6	53401	160000	2	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	0	6	19	5	5	53401	160000	0	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	3	10110	0	5	19	5	5	53401	160000	0	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	0	5	19	5	5	53401	160000	0	80100	53405	53405	53405	53405	53405
160204	53404	400	0	1	1	0	1	37	304	160178	160177	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160273	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10113	0	7	34	6	6	53401	160000	0	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	6	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	0	5	19	6	6	53401	160000	0	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	512	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	0	5	19	6	5	53401	160000	0	80100	53405	53405	53405	53405	53460
160204	53404	400	0	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	0	6	19	4	6	53401	160000	0	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	512	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	0	6	19	6	5	53401	160000	0	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	10110	6	5	19	5	6	53401	160000	0	80100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53380	399	0	0	0	0	43	25	160010	160010	160010	1029388	0	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	6	10022	8	2	1	21	19	2	1	1	19	9	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	64	25	160010	160076	160010	1029388	2	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	8	4	1	9	19	2	1	1	19	9	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	43	25	160010	160010	160010	1029388	0	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	8	4	1	9	19	2	1	1	19	9	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	49	25	160010	160010	160010	1029388	1	1	0	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	2	4	0	0	10022	8	4	1	19	19	26	1	2	7	19	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	49	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	8	4	1	19	19	2	1	1	9	19	53649	160000	20	11	80010	53375	53375	53375	53663	53375
160024	53374	400	0	1	1029	0	43	25	160010	160010	160083	1029388	2	1	5	49	50294	53374	53374	33377	0	16	33442	160010	160241	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	8	5	1	19	19	2	1	1	9	19	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	0	70	25	160010	160010	160010	1029388	0	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10024	11	6	2	7	19	4	2	2	19	9	53370	160000	40	20	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	49	25	160010	160010	160010	1029388	0	1	5	49	50294	53374	53374	33331	0	3	33372	160010	160020	160020	53411	52	1	1	160021	10	9	10	160010	10	0	0	0	3	10022	8	5	1	19	19	2	1	1	19	9	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	8	5	1	9	19	2	1	1	19	7	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	0	0	708	25	160010	160010	160010	1029388	0	1	5	49	50294	53374	53374	33331	0	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10024	11	6	2	19	19	4	2	2	7	19	53370	160000	40	20	80010	53375	53375	53375	53375	53375

Test 7: throughput

Count: 4

Code:

  fcmp s0, s0
  ngcs w0, w4
  ngcs w1, w4
  ngcs w2, w4
  ngcs w3, w4

Initialization

  mov x4, 5
  mov x5, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13415	101	0	45	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	5538	3353	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	45	45	25	50100	40100	10000	40100	10000	587442	80000	1	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	15	45	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	3	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	5538	3353	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	45	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	5538	3081	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13550	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	24	45	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	5538	3342	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	285	45	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	5553	3342	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	5553	3081	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	45	25	50100	40100	10000	40100	10000	587442	80000	1	13383	13412	13412	5553	3353	3	7146	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13383	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	3	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	3	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	101	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	48	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	3140	0	1	19	1	1	13379	40000	40010	13383	13383	13383	13383	13383

NGCS (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations