Firestorm: SUBS (uxtw, 32-bit) measurements

Code:

  subs w0, w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	9	103	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	3	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	73	0	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	76	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	3	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10207	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	129	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	1899	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	3	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	204	61	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	346	9920	25	10100	10100	10100	647152	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	168	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20404	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	124	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10082	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	1	3	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	1	0	82	9920	25	10126	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	15	3	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	1088	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	8	45	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	162	82	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	93	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	198	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	2	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	483	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20406	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	35	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	1	0	156	0	61	9918	25	10010	10010	10010	647246	1	49	7002	10083	10035	8678	9	8780	10010	10117	20020	10035	40	1	1	10021	10	9	10	10010	10	1	0	2	875	640	2	27	2	2	10031	10024	10010	10036	10036	10036	10036	10036
10024	10035	75	0	1	156	0	371	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20268	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10084	10083	10036	10036	10036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, uxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	149	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	7	3	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	3	3	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	60	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	151	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	4	3	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	5	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	2	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	4	0	1	1	1	1320	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	2	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	387	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	1	30	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	48	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	450	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	429	89	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, uxtw
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	42	81	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20067	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	9	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	1	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	149	0	0	0	0	0	9	0	369	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	0	0	18	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	480	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	18	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	0	0	6	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	24	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	4	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	24	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20407	30165	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, uxtw
  subs w1, w8, w9, uxtw
  subs w2, w8, w9, uxtw
  subs w3, w8, w9, uxtw
  subs w4, w8, w9, uxtw
  subs w5, w8, w9, uxtw
  subs w6, w8, w9, uxtw
  subs w7, w8, w9, uxtw

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26763	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	1	5112	2	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	26	0	9	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	1	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26781	26793	16684	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	200	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736
80204	26735	201	0	0	0	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	23655	26735	26735	16672	0	3	16690	80100	80200	160200	26735	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	5112	1	19	1	1	2	26731	80000	80100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26722	200	0	0	0	0	0	525	0	291	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	4	2	6	5020	8	18	2	6	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	18	2	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	18	2	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	35	25	80273	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80222	160020	26705	39	1	1	80021	10	9	10	80010	10	0	2	0	0	0	0	5020	2	18	2	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	199	0	0	0	0	0	0	0	77	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	2	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	2	18	2	4	26702	80000	80010	26706	26706	26706	26706	26797
80024	26705	200	0	0	0	0	0	0	0	917	25	80010	80010	80010	401361	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26844	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	2	18	2	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	13	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	35	4	2	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	3	18	4	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	2	24	0	35	46	80141	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	18	4	4	26702	80000	80010	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	0	0	0	35	25	80010	80010	80010	400050	49	23625	26705	26705	16665	0	3	16683	80010	80020	160020	26705	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	4	18	2	4	26702	80000	80010	26706	26706	26706	26706	26706

SUBS (uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations