Firestorm: STUR (32-bit) measurements

Code:

  stur w0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	549	4	0	19	1	527	16	16	0	25	1000	1000	1000	22832	0	542	542	364	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1014	14	36	1016	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	551
1004	553	4	0	3	1	527	16	16	0	25	1000	1000	1000	22424	0	542	551	355	3	409	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	8	1002	2	34	73	1	16	1	1	548	1000	543	543	551	552	552
1004	542	4	0	3	1	527	16	16	2	25	1000	1000	1000	22808	0	542	542	362	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	8	1002	2	34	73	1	16	1	1	547	1000	543	543	550	551	550
1004	542	4	6	9	1	535	16	16	0	25	1000	1000	1000	22760	0	542	542	355	3	407	1000	1000	2000	586	542	1	1	1001	1000	1000	1000	0	34	1002	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	551	552
1004	542	4	18	3	0	527	16	16	0	25	1000	1000	1000	22856	0	542	551	355	3	409	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	8	1002	2	34	73	1	16	1	1	547	1000	543	551	552	543	543
1004	542	5	0	3	1	527	16	16	0	25	1000	1000	1000	22424	0	551	542	363	3	400	1000	1000	2000	550	542	1	1	1001	1000	1000	1000	0	34	1002	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	550	551
1004	542	4	0	3	0	534	16	16	0	25	1000	1000	1000	22856	0	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	2	1002	2	34	73	1	16	1	1	539	1000	543	543	551	552	552
1004	542	4	21	9	0	527	16	16	0	25	1000	1000	1000	22424	0	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	551
1004	549	4	21	3	1	527	16	16	0	25	1000	1000	1000	22808	0	542	542	362	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	550
1004	542	4	6	3	0	527	16	16	0	25	1000	1000	1000	22424	1	542	542	355	3	408	1000	1000	2000	542	550	1	1	1001	1000	1000	1000	0	34	1002	5	1002	2	34	73	1	16	1	1	546	1000	551	543	543	543	543

Count: 8

Code:

  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40047	300	1	0	1	0	0	18	1	0	1	40037	16	16	5	25	80100	100	80000	100	80000	500	1839933	0	49	36974	40054	40047	29960	3	30012	80100	200	80000	200	160000	40052	32007	1	1	80201	100	99	100	80000	100	80000	100	80014	15	44	1	0	80016	0	0	24	80000	14	0	14	0	0	5110	1	16	1	1	40051	80000	100	40054	40055	40055	40048	40053
80204	40054	300	1	0	1	0	0	14	1	0	1	40038	16	16	2	25	80100	100	80000	100	80000	500	1839908	1	49	36967	40063	40052	29965	3	30012	80100	200	80000	200	160000	40048	32005	1	1	80201	100	99	100	80000	100	80000	100	80014	15	0	0	1	80014	1	0	28	80002	14	43	14	0	0	5110	1	16	1	1	40051	80000	100	40053	40055	40048	40048	40048
80204	40054	300	1	0	0	1	0	19	0	0	1	40032	16	16	6	25	80100	100	80000	100	80432	500	1840439	0	49	36974	40047	40047	29960	3	30012	80100	200	80000	200	160000	40052	32006	1	1	80201	100	99	100	80000	100	80000	100	80016	14	0	0	0	80016	4	0	142	80002	16	44	14	0	0	5110	1	16	1	1	40044	80000	100	40054	40055	40048	40064	40052
80204	40054	300	1	1	1	1	0	19	1	0	1	40039	16	16	0	25	80100	100	80000	100	80000	500	1840460	0	49	36974	40052	40054	29967	3	30012	80100	200	80000	200	160000	40053	32000	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	1	80016	1	0	17	80002	16	44	14	0	1	5110	1	16	1	1	40051	80000	100	40052	40055	40053	40056	40053
80204	40054	300	1	0	0	0	0	17	1	0	1	40032	0	16	1	25	80100	100	80000	100	80000	500	1839908	1	49	36973	40064	40047	29965	3	30012	80100	200	80000	200	160000	40052	32005	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	0	80014	1	0	21	80002	16	44	14	0	0	5110	1	16	1	1	40049	80000	100	40064	40055	40049	40048	40048
80204	40052	300	1	1	0	0	90	17	1	0	1	40037	16	16	5	25	80100	100	80000	100	80000	500	1839692	1	49	36968	40047	40054	29960	3	30010	80100	200	80000	200	160000	40054	32000	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	0	80014	0	0	19	80002	14	44	14	1	0	5110	1	16	1	1	40051	80000	100	40055	40053	40055	40048	40055
80204	40047	299	1	1	1	1	0	14	1	0	1	40039	16	0	2	25	80100	100	80000	100	80000	500	1839933	0	49	36974	40052	40054	29967	3	30012	80100	200	80000	200	160000	40047	32007	1	1	80201	100	99	100	80000	100	80000	100	80016	14	0	0	0	80016	48	0	54	80002	16	44	14	1	0	5110	1	16	1	1	40051	80000	100	40048	40064	40055	40053	40048
80204	40054	300	1	1	0	0	0	20	0	0	1	40038	16	16	2	25	80100	100	80000	100	80216	500	1839933	0	49	36974	40054	40047	29967	3	30022	80100	200	80000	200	160000	40054	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	15	44	0	3	80016	0	0	159	80000	16	44	14	0	0	5110	1	16	1	1	40060	80000	100	40048	40054	40055	40055	40048
80204	40055	300	1	1	0	1	0	14	0	1	1	40039	16	16	1	25	80100	100	80000	100	80000	500	1839692	1	49	36974	40052	40054	29967	3	30012	80100	200	80000	200	160000	40053	32007	1	1	80201	100	99	100	80000	100	80000	100	80014	15	44	0	0	80016	0	0	107	80002	14	0	14	0	0	5110	1	16	1	1	40049	80000	100	40065	40055	40049	40055	40048
80204	40047	300	1	1	0	0	6	20	0	1	1	40039	16	16	1	25	80100	100	80000	100	80000	500	1840004	0	49	36972	40054	40063	29967	3	30009	80100	200	80000	200	160000	40055	32016	1	1	80201	100	99	100	80000	100	80000	100	80014	16	44	0	1	80016	0	0	152	80002	16	0	14	1	0	5110	1	16	1	1	40051	80000	100	40054	40055	40055	40055	40053

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40049	300	0	9	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	1	49	36962	0	40040	40042	29977	3	30022	80010	20	80000	20	160280	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	55	8	80002	2	34	5020	1	16	0	1	1	40039	80000	10	40051	40043	40050	40043	40043
80024	40042	300	0	3	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	49	36960	0	40042	40042	29977	3	30020	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	52	6	80002	2	0	5020	1	16	0	1	1	40037	80000	10	40052	40041	40052	40041	40043
80024	40042	300	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	1	49	36962	0	40042	40042	29977	3	30030	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	80002	0	5	80002	2	34	5020	1	16	0	1	1	40037	80000	10	40043	40041	40041	40043	40043
80024	40040	299	0	3	0	0	40025	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	49	36962	0	40040	40042	29984	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	1	102	80002	0	34	5020	1	16	0	1	1	40037	80000	10	40051	40041	40043	40043	40041
80024	40042	300	0	3	1	0	40034	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	0	40042	40042	29975	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	0	6	80002	2	34	5020	1	16	0	1	2	40039	80000	10	40043	40043	40043	40043	40041
80024	40040	300	0	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839760	1	49	36970	0	40042	40049	29977	3	30022	80010	20	80000	20	160000	40040	40050	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	16	59	80002	2	34	5020	1	16	1	1	1	40039	80000	10	40043	40041	40043	40043	40051
80024	40042	300	0	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	49	36962	0	40042	40051	29986	3	30022	80010	20	80000	20	160000	40051	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	45	11	80002	2	34	5020	1	16	0	1	1	40039	80000	10	40043	40052	40043	40052	40041
80024	40042	299	0	9	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36962	0	40050	40040	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	55	8	80002	0	34	5020	1	16	0	1	1	40039	80000	10	40041	40043	40041	40043	40054
80024	40042	300	6	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1853695	1	49	36962	0	40042	40042	29975	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	29	80002	7	17	80000	2	34	5020	1	16	0	1	1	40039	80000	10	40041	40043	40043	40041	40041
80024	40051	300	6	3	1	0	40036	16	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36971	0	40042	40051	29977	3	30020	80010	20	80000	20	160000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	80002	37	0	80000	2	34	5020	1	16	0	1	1	40039	80000	10	40043	40051	40043	40051	40041

STUR (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations