Firestorm: CSEL (64-bit) measurements

Code:

  csel x0, x0, x1, hi

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	2	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	82	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	104	1	1	1001	1000	1000	0	0	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1091	3000	1035	104	1	1	1001	1000	1000	0	1	0	73	1	27	1	1	990	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  csel x0, x0, x1, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	943	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	60	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	9	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	39	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	21	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	1	66	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	156	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	78	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	710	2	27	2	2	9992	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	124	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	3	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	126	9918	25	10010	10010	10010	647246	0	49	6955	10035	10079	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	1	0	0	640	2	27	2	4	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	355	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10022	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	528	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	103	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  csel x0, x1, x0, hi

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	710	1	42	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	2	63	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	87	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	57	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	102	1	1	10201	100	99	100	10100	10100	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	272	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	82	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10067	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	0	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	104	1	1	10021	10	9	10	10010	10010	1	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 1->4

Chain cycles: 1

Code:

  csel x0, x1, x2, hi
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	103	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	15	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	84	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20082	20081	20081	20082	20082
20204	20080	150	0	0	0	183	19926	25	20200	20200	20200	1297650	0	49	17002	20035	20035	17406	3	17481	20200	20200	40200	20035	104	2	1	20201	100	99	20100	10000	0	2	805	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	104	1	1	20201	100	99	20100	10000	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	149	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	24	0	536	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	1460	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	17000	20126	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	2	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	346	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	104	1	1	20021	10	9	20010	10000	0	0	0	0	1270	2	27	2	2	19995	20010	10010	20036	20036	20036	20036	20036

Test 5: throughput

Count: 8

Code:

  csel x0, x8, x9, hi
  csel x1, x8, x9, hi
  csel x2, x8, x9, hi
  csel x3, x8, x9, hi
  csel x4, x8, x9, hi
  csel x5, x8, x9, hi
  csel x6, x8, x9, hi
  csel x7, x8, x9, hi

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26797	200	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	35	0	0	0	5110	2	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	28	0	0	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	201	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	25	0	3	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	114	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	6	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	13	0	0	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	2721	25	80100	80100	80100	479799	0	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	11	0	0	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	1	0	21	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	36	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	26	0	1393	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737
80204	26736	200	0	0	0	0	0	0	0	93	25	80100	80100	80100	479799	1	49	23656	26736	26736	16672	3	16691	80100	80200	240200	26736	66	1	1	80201	100	99	100	80100	80100	0	0	0	0	0	15	0	5110	1	19	1	1	26732	80000	80100	26737	26737	26737	26737	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26711	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26742	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	5	18	0	4	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	57	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	4	18	0	2	5	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	4	18	0	4	2	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	4	18	0	4	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	2	18	0	2	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	2	18	0	2	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	2	18	0	5	5	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	199	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	2	18	0	2	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	1	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	0	2	18	0	2	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	240020	26706	66	1	1	80021	10	9	10	80010	80010	0	0	0	0	0	0	0	0	5020	2	4	18	0	3	5	26702	80000	80010	26707	26707	26707	26707	26707

CSEL (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations