Firestorm: LDURSW measurements

Code:

  ldursw x0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	1	0	0	1	1	41	1	0	2	379	2	12	18	16	25	1000	1000	1000	14774	374	374	217	3	232	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	0	39	1000	0	0	0	39	1039	6	1	35	39	0	0	73	2	16	2	2	391	6	0	4	1000	390	395	390	395	390
1004	389	3	0	0	0	0	1	45	0	0	2	374	0	12	12	16	25	1000	1000	1000	14838	389	394	212	3	232	1000	1000	1000	389	56	1	1	1001	1000	1000	1	1000	0	0	1039	0	0	0	0	1035	6	1	35	0	0	0	73	2	16	2	2	386	10	6	4	1000	395	375	395	395	380
1004	394	3	0	0	0	0	0	45	1	0	2	359	2	12	18	0	25	1000	1000	1000	15609	399	399	221	3	240	1000	1000	1000	399	82	1	1	1001	1000	1000	0	1020	19	0	1058	1	0	0	22	1000	6	0	35	43	0	0	73	2	16	2	2	391	6	0	4	1000	395	390	390	390	390
1004	391	3	1	0	0	0	0	41	1	0	0	379	0	12	12	16	25	1000	1000	1000	15318	399	399	204	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1020	20	42	1019	0	0	1	59	1038	6	1	39	39	0	0	73	2	16	2	2	391	10	6	4	1000	395	395	390	395	395
1004	394	3	1	0	0	1	1	45	1	0	2	379	2	0	12	16	25	1000	1000	1000	15357	403	381	204	3	257	1000	1000	1000	399	64	1	1	1001	1000	1000	0	1019	19	42	1056	1	0	0	21	1038	6	1	35	39	0	0	73	2	16	2	2	391	0	0	4	1000	395	395	395	395	395
1004	394	3	1	0	0	1	0	45	0	0	2	379	0	12	18	16	25	1000	1000	1000	15288	374	394	197	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1000	0	39	1000	0	0	0	39	1035	0	0	35	43	0	0	73	2	16	2	2	391	6	0	4	1000	395	395	395	395	395
1004	394	3	1	0	0	0	0	66	1	0	2	367	0	18	18	14	25	1000	1000	1000	15362	394	374	212	3	247	1000	1000	1000	389	56	1	1	1001	1000	1000	0	1000	0	39	1040	0	0	0	42	1051	6	1	39	43	0	0	73	2	16	2	2	391	10	10	0	1000	375	375	375	395	382
1004	383	3	1	1	1	0	0	197	1	0	3	384	2	18	18	14	25	1000	1000	1000	15062	394	389	217	3	252	1000	1000	1000	374	71	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	35	1000	0	1	39	43	0	0	73	2	16	2	2	394	0	0	4	1000	395	395	395	396	375
1004	374	3	0	0	0	0	0	45	1	0	2	359	2	0	12	0	25	1000	1000	1000	15375	399	398	224	3	239	1000	1000	1000	398	64	1	1	1001	1000	1000	0	1019	20	42	1035	0	0	0	0	1000	6	1	0	0	0	0	73	2	16	2	2	391	10	0	4	1000	395	395	395	375	375
1004	374	3	0	0	0	0	0	0	0	0	2	379	2	0	12	15	25	1000	1000	1000	14838	394	394	216	3	252	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1000	0	39	1057	0	0	1	62	1038	6	1	57	42	19	0	73	2	16	2	2	396	9	0	2	1000	382	400	399	400	390

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursw x0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	524	1	0	0	1000	1	0	70039	69782	59710	25	40104	30103	10002	30100	10000	616175	3341470	1	49	66974	0	70054	70054	64650	3	64964	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	10000	1	0	0	2610	2	71	1	1	69817	30003	13	0	0	10000	30100	70036	70036	70055	70052	70060
40204	70054	525	0	0	0	901	1	0	70020	69782	59713	25	40104	30103	10000	30100	10000	616014	3342398	1	49	66971	0	70035	70051	64650	3	64956	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69798	30000	13	13	10	10000	30100	70055	70036	70055	70055	70036
40204	70054	525	0	0	0	1	1	0	70020	69790	59695	25	40100	30103	10000	30100	10000	616041	3342398	1	49	66955	0	70035	70035	64650	3	64958	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	15	1	10000	1	0	0	2610	1	71	1	1	69814	30003	13	10	13	10000	30100	70036	70052	70052	70036	70153
40204	70054	524	0	0	0	897	1	0	70020	69785	59713	25	40104	30100	10001	30100	10000	616175	3342398	1	49	66971	0	70035	70035	64650	3	64966	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69818	30003	13	0	13	10000	30100	70036	70055	70036	70036	70037
40204	70054	524	0	0	0	1	1	0	70039	69782	59695	25	40104	30100	10001	30100	10000	616175	3341470	1	49	66955	0	70051	70051	64650	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	2610	1	71	1	1	69798	30003	0	10	10	10000	30100	70052	70055	70055	70055	70055
40204	70054	525	0	0	0	1	0	1	70020	69785	59710	25	40100	30103	10001	30100	10000	616175	3342254	1	49	66974	0	70054	70054	64650	3	64942	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	0	1	0	2610	1	71	1	1	69817	30003	13	0	0	10000	30100	70036	70055	70055	70036	70055
40204	70054	524	0	0	0	0	0	0	70020	69782	59713	25	40104	30103	10001	30100	10000	616041	3341470	1	49	66974	0	70054	70051	64650	3	64941	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	2610	1	17	1	1	69798	30003	13	10	0	10000	30100	70055	70036	70055	70036	70055
40204	70035	525	0	0	0	0	0	0	70039	69785	59695	25	40104	30103	10000	30100	10000	616041	3341470	1	49	66955	0	70054	70054	64650	3	64960	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	71	1	1	69814	30000	10	13	0	10000	30100	70055	70055	70036	70052	70036
40204	70054	524	0	0	0	835	0	0	70039	69785	59713	25	40104	30103	10001	30100	10000	616041	3343049	1	49	66974	0	70054	70051	64650	3	64963	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	2610	1	71	1	2	69798	30003	13	10	13	10000	30100	70060	70098	70112	70036	70055
40204	70054	524	0	0	0	889	0	1	70020	69764	59713	25	40104	30103	10001	30100	10000	616175	3341470	1	49	66974	0	70038	70035	64631	3	64954	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	0	2610	1	71	1	1	69798	30003	0	0	0	10000	30100	70052	70036	70055	70055	70055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	525	0	0	1	1	1	1	0	70036	69778	59808	25	40014	30013	10001	30010	10000	617068	3342254	0	49	66974	70054	70054	64653	3	64979	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	0	10003	1	1	2520	2	71	1	1	69817	30003	10	10	10	10000	30010	70036	70055	70055	70036	70052
40024	70054	525	0	0	0	0	70	0	0	70039	69775	59818	25	40014	30013	10000	30010	10000	617068	3342398	0	49	66974	70035	70054	64672	3	64979	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	5	0	10000	0	0	2520	1	71	1	1	69814	30003	13	0	13	10000	30010	70055	70055	70055	70060	70067
40024	70054	524	0	1	0	0	1	0	0	70039	69778	59796	25	40010	30013	10001	30010	10000	616991	3342254	0	49	66974	70035	70054	64672	3	64979	40010	30020	10000	60020	10000	70091	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	0	0	10000	0	0	2520	1	71	1	1	69798	30003	13	0	13	10000	30010	70055	70055	70036	70055	70102
40024	70054	525	0	0	0	0	1	0	0	70039	69778	59823	25	40014	30010	10001	30010	10000	617018	3342398	0	49	66974	70035	70035	64672	3	64979	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	1	1	9	10000	1	1	2520	1	71	1	1	69798	30003	13	10	10	10000	30010	70057	70036	70052	70036	70059
40024	70054	525	0	0	0	0	1	1	0	70039	69778	59803	25	40014	30013	10001	30010	10000	617018	3341470	0	49	66974	70054	70054	64672	3	64979	40010	30020	10000	60020	10000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	4	0	10000	0	0	2520	1	71	1	1	69817	30003	13	0	13	10000	30010	70055	70055	70036	70055	70059
40024	70054	524	0	0	0	0	0	0	0	70036	69778	59695	25	40010	30013	10001	30010	10000	617068	3341470	0	49	66971	70035	70051	64653	3	64960	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	4	0	10000	1	1	2520	1	71	1	1	69817	30003	13	10	13	10000	30010	70055	70055	70055	70055	70057
40024	70054	524	0	0	0	0	1	0	0	70039	69778	59710	25	40014	30013	10001	30010	10000	617018	3341470	0	49	66955	70035	70051	64672	3	64960	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	3	0	10000	1	1	2520	1	71	1	1	69817	30003	13	13	13	10000	30010	70055	70036	70055	70052	70059
40024	70051	524	0	0	0	0	1	1	0	70020	69778	59695	25	40014	30013	10001	30010	10000	617018	3342203	0	49	66955	70051	70051	64672	3	64979	40010	30020	10000	60020	10000	70044	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	0	10000	0	4	0	10000	1	1	2520	1	71	1	1	69817	30003	13	13	10	10000	30010	70055	70055	70036	70055	70056
40024	70051	524	0	0	0	0	1	0	0	70039	69778	59730	25	40010	30010	10000	30010	10000	617018	3342398	0	49	66974	70054	70035	64653	3	64979	40010	30020	10000	60020	10000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10012	0	1	6	10000	0	1	2520	1	71	1	1	69798	30003	0	10	13	10000	30010	70055	70036	70074	70036	70056
40024	70054	525	0	1	1	0	0	1	0	70039	69743	59713	25	40014	30013	10000	30010	10000	617068	3342398	0	49	66974	70054	70054	64653	3	64979	40010	30020	10000	60020	10000	70054	35	1	1	40021	10	9	10	10000	30010	10000	10	10000	1	10000	0	4	0	10000	0	1	2520	1	71	1	1	69814	30003	13	13	0	10000	30010	70055	70055	70036	70055	70052

Test 3: throughput

Count: 8

Code:

  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]
  ldursw x0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	0	0	0	41	1	0	1	26707	2	18	18	0	25	80100	100	80000	100	80000	500	1167808	1	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26724	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	1	0	35	80035	6	1	35	39	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	41	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80000	500	1167790	0	49	23684	26742	26722	16645	3	16680	80100	200	80000	200	80000	26726	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	0	80035	1	0	35	80035	6	1	35	39	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	41	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80000	500	1167808	1	49	23642	26722	26722	16630	3	16680	80100	200	80000	200	80000	26731	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	35	80035	6	1	35	39	0	1	5110	1	16	1	1	26726	6	0	0	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	41	1	0	1	26707	2	18	18	79	25	80100	100	80000	100	80000	500	1166818	0	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26730	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80167	0	0	35	80035	6	1	35	39	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26723	26723	26723	26729
80204	26722	200	0	0	0	0	41	1	0	1	26692	2	18	18	12	25	80100	112	80000	100	80000	500	1167808	0	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26830	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	0	80035	0	0	35	80035	6	1	35	39	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26813	26723	26742	26708
80204	26715	200	0	0	0	0	41	0	0	1	26707	2	0	18	11	25	80100	100	80000	100	80000	500	1159747	0	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26725	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	35	80035	6	1	35	39	0	0	5110	1	16	1	1	26728	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	41	0	0	1	26707	2	18	18	12	25	80100	100	80000	100	80000	500	1166818	0	49	23642	26723	26722	16645	3	16680	80100	200	80000	200	80000	26736	71	1	1	80201	100	99	100	80000	100	80000	0	100	80132	2	39	0	80035	0	0	38	80035	6	1	35	39	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	1	1	0	41	1	0	1	26707	0	18	18	12	25	80100	100	80000	100	80000	500	1166525	0	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26725	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	35	80035	6	1	35	39	0	0	5110	3	16	1	1	26708	6	6	2	80000	100	26723	26723	26723	26723	26723
80204	26722	200	0	0	0	0	41	0	0	1	26707	2	18	18	11	25	80100	100	80000	100	80000	500	1167808	0	49	23642	26722	26707	16645	3	16680	80100	200	80000	200	80000	26730	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	0	80035	0	0	35	80035	6	1	35	39	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26723	26723	26708	26723
80204	26722	200	0	0	0	0	41	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80000	500	1167094	1	49	23645	26722	26722	16648	9	16680	80100	200	80000	200	80000	26733	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	35	80035	6	1	35	39	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26723	26723	26723	26708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	1	0	1	1	0	0	21	0	2	26721	2	7	7	111	25	80010	10	80000	10	80000	50	1168286	49	23657	26736	26736	16681	3	16716	80010	20	80000	20	80000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	43	0	80059	1	0	1	61	80039	6	1	59	43	19	1	5020	0	7	16	5	6	26733	13	13	5	80000	10	26855	26750	26808	26746	26737
80024	26736	200	1	0	0	1	0	0	67	0	2	26721	3	7	7	23	25	80010	10	80000	10	80000	50	1167298	49	23656	26736	26736	16682	3	16717	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	0	80058	0	0	0	21	80040	6	1	58	43	19	1	5020	0	4	16	4	4	26734	13	13	5	80000	10	26862	26748	26810	26747	26738
80024	26736	200	1	1	1	0	0	0	21	1	3	26721	2	7	7	22	25	80010	10	80000	10	80000	50	1166960	49	23657	26714	26715	16681	3	16716	80010	20	80000	20	80000	26715	86	1	1	80021	10	9	1	10	80000	10	80000	0	10	80020	19	43	0	80059	0	0	0	60	80040	6	1	59	43	19	0	5020	6	5	16	5	4	26733	13	13	5	80000	10	26716	26737	26737	26738	26741
80024	26736	200	1	0	0	1	0	0	21	1	3	26721	3	7	7	19	25	80010	10	80000	10	80000	50	1166960	49	23657	26714	26715	16681	3	16716	80010	20	80000	20	80000	26736	86	1	1	80021	10	9	1	10	80000	10	80000	0	10	80019	20	43	0	80059	0	0	1	21	80040	6	1	59	0	19	0	5020	0	4	16	4	4	26992	13	13	5	80000	10	26844	26741	26740	26743	26738
80024	26737	200	1	0	1	1	0	0	67	0	3	26721	3	0	7	25	25	80010	10	80000	10	80000	50	1167736	49	23656	26736	26737	16681	3	16716	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	0	80060	0	4	6	74	80039	6	1	60	43	19	0	5020	0	3	16	5	5	26733	13	13	5	80000	10	26916	26742	26742	26742	26740
80024	26737	200	1	1	0	0	0	0	66	1	2	26700	2	7	7	19	25	80010	10	80000	10	80000	50	1167791	49	23886	26740	26772	16659	3	16694	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	43	0	80059	1	0	3	61	80039	6	1	58	43	19	2	5020	0	4	16	4	4	26733	13	13	5	80000	10	26742	26740	26747	26756	26737
80024	26736	200	1	0	1	0	0	0	67	0	2	26721	0	7	7	21	25	80010	10	80000	10	80000	50	1165304	49	23656	26736	26737	16681	3	16716	80010	20	80000	20	80000	26737	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	0	80060	0	0	0	60	80040	6	1	59	0	18	0	5020	0	4	16	5	6	26769	13	13	0	80000	10	26742	26813	26739	26747	26737
80024	26714	200	1	1	1	0	0	0	21	1	1	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1165304	49	23656	26737	26736	16660	3	16717	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	21	0	0	80059	0	0	0	61	80039	0	1	59	43	19	2	5020	0	5	16	6	6	26712	13	13	5	80000	10	26816	26743	26780	26726	26737
80024	26715	200	1	0	0	0	0	0	67	1	3	26721	3	7	7	32	25	80010	10	80000	10	80000	50	1167791	49	23635	26736	26736	16681	3	16694	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	0	80058	1	0	0	21	80000	6	0	19	0	19	0	5020	0	6	16	5	5	26734	0	13	5	80000	10	26847	26744	26852	26748	26738
80024	26715	200	1	1	1	1	0	0	67	1	2	26721	1	7	0	23	25	80010	10	80000	10	80000	50	1168286	49	23657	26736	26736	16682	3	16717	80010	20	80000	20	80000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	0	80019	0	1	1	61	80040	6	1	59	43	19	0	5020	0	4	16	4	4	26712	13	13	0	80000	10	26738	26805	26743	26826	26737

LDURSW

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations