Firestorm: B measurements

Code:

  b .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	51	60	6d	6e	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	1936	15	0	0	11	99	2018	0	2004	2044	3	10	2008	2054	1	1	1001	1000	1000	0	0	2006	642	875	521	493	1985	1975	1931	2005	1989	2043
1004	1998	15	0	0	11	87	2014	1	1814	2008	3	10	2014	2004	1	1	1001	1000	1000	0	0	1940	414	1139	404	487	1903	2157	1987	1879	2067	1997
1004	1950	15	0	0	5	93	1828	1	1836	2160	3	10	1976	1992	1	1	1001	1000	1000	0	0	1952	487	979	526	476	2019	2043	2071	1969	2143	1983
1004	2008	15	0	0	12	80	2072	1	1958	2084	3	10	2084	1968	1	1	1001	1000	1000	0	0	1968	519	939	527	494	2015	1993	2009	1871	2153	2003
1004	1960	15	0	0	11	68	1998	0	1994	2042	3	10	1972	2044	1	1	1001	1000	1000	0	0	1942	477	1029	428	523	2029	2045	1967	1901	2063	2091
1004	1980	15	0	0	7	93	2030	0	1954	1960	3	10	1892	2102	1	1	1001	1000	1000	0	0	1992	452	1009	482	489	1951	1971	2015	1913	2067	2079
1004	1996	14	0	0	7	93	1958	1	2058	1986	3	10	1984	2004	1	1	1001	1000	1000	0	0	1946	428	961	461	504	2059	1953	2083	2057	1961	1965
1004	2098	15	0	0	12	99	1956	1	2028	1890	3	10	1860	2074	1	1	1001	1000	1000	0	0	2070	463	983	424	524	1921	2053	1993	2079	2079	2063
1004	2030	13	0	0	14	99	2026	1	2046	1960	3	10	1892	2068	1	1	1001	1000	1000	0	0	1980	480	951	460	458	1987	1961	1965	2067	1969	1909
1004	2002	15	0	0	11	68	1962	0	1978	2020	3	10	1966	2088	1	1	1001	1000	1000	0	0	1970	415	991	387	481	1937	2019	1989	2031	1889	2069

Count: 8

Code:

  b .+4
  b .+4
  b .+4
  b .+4
  b .+4
  b .+4
  b .+4
  b .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0097

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	81254	606	0	0	0	0	0	0	0	0	28	80275	100	100	100	500	0	49	77684	80768	80766	6	10	100	200	200	80776	64730	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	3	0	1	1	1	80755	414	675	321	324	80775	0	100	80767	80769	80771	80765	80767
80204	80798	605	1	0	1	0	0	0	0	0	28	80267	100	100	100	500	0	49	77680	80768	80760	6	10	100	200	200	80764	64716	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	6	0	1	1	1	80741	318	645	315	319	80769	0	100	80769	80771	80771	80775	80779
80204	80776	605	1	0	1	0	0	0	162	0	28	80263	100	100	100	500	0	49	77708	80798	80794	6	10	100	200	200	80798	64756	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	6	0	1	1	1	80739	315	635	314	314	80759	0	100	80779	80765	80763	80765	80771
80204	80772	605	1	0	1	0	0	0	0	0	28	80267	100	100	100	500	0	49	77684	80758	80762	6	10	100	200	200	80766	64724	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	3	0	1	1	1	80743	314	637	311	313	80769	0	100	80767	80761	80769	80769	80769
80204	80774	605	1	0	1	0	0	0	0	0	693	80263	100	100	100	500	0	49	77692	80772	80768	6	10	100	200	200	80772	64730	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	9	0	1	1	1	80747	314	641	314	315	80769	0	100	80775	80765	80771	80769	80773
80204	80784	605	1	0	1	0	0	0	0	0	28	80263	100	100	100	500	0	49	77680	80764	80770	6	10	100	200	200	80762	64724	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	3	0	1	1	1	80747	317	647	315	316	80769	0	100	80769	80769	80771	80773	80773
80204	80780	605	1	0	1	0	0	0	0	0	28	80263	100	100	100	500	0	49	77686	80768	80758	6	10	100	200	200	80768	64718	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	3	0	1	1	1	80771	323	669	326	328	80783	0	100	80793	80795	80793	80793	80789
80204	80774	605	1	0	1	0	0	0	0	0	28	80267	100	100	100	500	0	49	77702	80782	80786	6	10	100	200	200	80776	64738	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	6	0	1	1	1	80757	319	647	319	317	80775	0	100	80773	80767	80769	80765	80763
80204	80802	605	1	0	1	0	0	0	0	0	28	80263	100	100	100	500	0	49	77692	80762	80766	6	10	100	200	200	80770	64718	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	3	0	1	1	1	80751	312	639	321	316	80773	0	100	80771	80775	80777	80781	80775
80204	80798	605	1	0	1	0	0	0	0	0	693	80277	100	100	100	500	0	49	77688	80772	80776	6	10	100	200	200	80772	64712	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	12	0	1	1	1	80791	318	643	314	320	80763	0	100	80769	80767	80769	80765	80771

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	240058	1798	1	0	0	0	0	0	0	17	336	239989	10	10	10	50	0	49	236962	0	240042	240044	6	10	10	20	20	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	3	0	1	1	1	240021	0	0	79833	160014	79954	80002	240041	0	10	240043	240045	240045	240043	240043
80024	240044	1798	2	0	0	0	0	81	0	14	172	239989	10	10	10	50	0	49	236962	0	240044	240044	6	10	10	20	20	239508	240042	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240019	0	0	80003	160016	79952	80004	239849	0	10	240041	240047	240047	240037	240045
80024	240048	1798	1	0	0	0	0	0	0	18	178	239991	10	10	10	50	1	49	236962	0	240104	240044	6	10	10	20	20	240042	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240021	0	0	80001	160016	79955	80002	240041	0	10	240045	240045	240043	240043	240043
80024	240044	1798	2	0	0	0	0	0	0	17	193	239991	10	10	10	50	0	49	236964	0	240042	240044	6	10	10	20	20	240042	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240021	0	0	80001	160016	79954	79904	240039	0	10	240045	239863	239509	240043	240045
80024	240042	1798	2	0	0	0	0	0	0	19	189	239816	10	10	10	50	0	49	236966	0	240044	240044	6	10	10	20	20	240042	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240019	0	0	80001	160016	79955	80000	240039	0	10	240045	240045	240043	240045	240045
80024	240069	1798	2	0	0	0	0	0	0	17	325	239991	10	10	10	50	0	49	236964	0	240044	240044	6	10	10	20	20	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240021	0	0	80000	160016	79953	80002	240041	0	10	240045	240045	240045	240045	240045
80024	240044	1798	2	0	0	0	0	0	0	17	214	239991	10	10	10	50	0	49	236964	0	240044	240044	6	10	10	20	20	240044	240042	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240021	0	0	80001	160016	79954	80002	240041	0	10	240045	240045	240045	240045	240045
80024	240044	1798	2	0	0	0	0	0	0	23	1997	239991	10	10	10	50	0	49	236962	0	240044	240112	6	10	10	20	20	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240021	0	0	80001	160016	79955	80002	240041	0	10	240045	240045	240045	240045	240045
80024	240044	1798	2	0	0	0	0	0	0	17	837	239991	10	10	10	50	0	49	236962	0	240044	240044	6	10	10	20	20	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	195	0	1	1	1	240021	0	0	80001	160016	79954	80002	240041	0	10	240045	240045	240045	240045	240045
80024	240042	1798	2	0	0	0	0	0	0	17	172	239991	10	10	10	50	0	49	236964	0	240044	240042	6	10	10	20	20	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	1	1	1	240021	0	0	80001	160016	79955	80002	240041	0	10	240045	240045	240045	240043	240045

B

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations