Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

NEGS (register, asr, 32-bit)

Test 1: uops

Code:

  negs w0, w0, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420351500611000186225200020001000126235020352035172931866100010001000203541111001100000732431119202000100020362036203620362036
100420351500611000186225200020001000126235020352035172931866100010001000203541111001100000731431119202000100020362036203620362036
1004203515001701000186225200020001000126235020352035172931866100010001000203541111001100000731431119202000100020362036203620362036
100420351600611000186225200020001000126235020352035172931866100010001000203541111001100000731431119202000100020362036203620362036
100420351500611000186225200020001000126235020352035172931866100010001000203541111001100003731431119202000100020362036203620362036
100420351500611000186225200020001000126235020352035172931866100010001000203541111001100000731431119202000100020362036203620362036
100420351500611000186225200020001000126235020352035172931866100010001000203541111001100000731431119202000100020362036203620362036
100420351600611000186225200020001000126235020352035172931866100010001000203541111001100000731431119202000100020362036203620362036
100420351500611000186225200020001000126235020352035172931866100010001000203541111001100000731431119202000100020362036203620362036
10042035150541241000186225200020001000126235120352035172931866100010001000203541111001100000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  negs w0, w0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
10204200351500053610000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150006110000198622520100201001010013051210491695520035200351858131872010100102001020020035411110201100991001010010000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351500841000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
100242003515007261000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036
10024200351509611000019862252001020010100101305229491695520035200351860331874010010100201002020035411110021109101001010640241221993020000100102003620036200362003620036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  negs w0, w1, asr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225000061100002989925301003010020107195624014926955300353003527391827486201072022420224300358511202011009910020100101000000011113191162998230000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014926955300353003527391827486201072022420224300358511202011009910020100101000000011113201162998330000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014924644300353003527391727486201072022420224300358511202011009910020100101000000011113201162998330000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014926955300353003527391727485201072022420224300358511202011009910020100101000000011113201162998230000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014926955300353003527391727486201072022420224300358511202011009910020100101000000011113200162998230000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014926955300353003527391727485201072022420224300358511202011009910020100101000000011113200162998230000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014926955300353003527391827486201072022420224300358511202011009910020100101000000011113191162998230000201003003630036300363003630036
2020430035224000061100002989925301003010020107195624014926955300353003527391727485201072022420224300358511202011009910020100101000000011113190162998330000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014926955300353003527391827485201072022420224300358511202011009910020100101000000011113191162998330000201003003630036300363003630036
2020430035225000061100002989925301003010020107195624014926955300353003527391727485201072022420224300358511202011009910020100101000000011113201162998330000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002430035225119761626701005429927217301873018620697195993804927364300353003527391327498200102002020020300358511200211091020010100102001270133112995930000200103003630036300363003630036
2002430035225088168100002989125300323001020010195628904926955300353003527391727498200102010920108300828511200211091020010100100001270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904926955300353003527391327498200102002020020300358511200211091020010100100031270141112995930000200103003630036300363003630036
200243003522500103100002989125300103001020010195628904926955300353003527391327498200102002020020300358511200211091020010100100001270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904927001300353003527391327498200102002020020300358511200211091020010100101001270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904926955300353003527391327498200102002020020300358511200211091020010100100001270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904926955300353003527391327498200102002020020300358511200211091020010100100001270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002020020300358511200211091020010100100001270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904926955300353003527391327498200102002020020300358511200211091020010100100001270133112995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002020020300358511200211091020010100100001270133112995930000200103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  negs w0, w8, asr #17
  negs w1, w8, asr #17
  negs w2, w8, asr #17
  negs w3, w8, asr #17
  negs w4, w8, asr #17
  negs w5, w8, asr #17
  negs w6, w8, asr #17
  negs w7, w8, asr #17
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020453507400000021058001348791291601371601378017634418904950333534145341443345290984335580176802888028853414391180201100991008010010000000011151230160053411160037801005341553415534155341553415
8020453414400000022588001348791291601371601378017634418904950334534145341443345290984335580176802888028853414391180201100991008010010000000011151240160053411160037801005341553415534155341553415
8020453414400000019258001348791291601371601378017634418904950334534145341443345290984335580176802888028853414391180201100991008010010000000011151240160053411160037801005341553415534155341553415
8020453413400000020298001348791291601371601378017634418904950334534145341443345290984335580176802888028853414391180201100991008010010000000011151240160053411160037801005341553415534155341553415
8020453414400000021708001348791251601001601008010034400054950330534105341043298290934336080100802008020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
8020453410400000021588000048741251601001601008010034400054950330534105341043298290934336080100802008020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
802045341040000002088000048741251601001601008010034400054950330534105341043298290934336080100802008020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
802045341040000002508000048741251601001601008010034400054950330534105341043298302434336080100804188020053467391180201100991008010010000000000051101241153390160000801005341153411534115341153411
8020453410400000021618000048741251601001601008010034400054950330534105341043298302434336080100802008020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411
8020453410400000020648000048741251601001601008010034400054950330534105341043298302434336080273802008020053410391180201100991008010010000000000051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800245338540000000346480000479462516001016001080010343813014950300533805338043290293634335280010800208002053380391180021109108001010000050401824111353360160000800105338153381533815338153381
8002453380399000001618000047946251600101600108001034381301495030053380533804329032513433528001080020800205338039118002110910800101000005020724111453360160000800105338153381533815338153381
80024533804000000011038000047946251600101600108001034381300495030053380533804329029363433528001080020800205338039118002110910800101000005020122491353360160000800105338153381533815338153381
800245338040000000121080000479462516001016001080010343813004950300533805338043290293634335280010800208022453380391180021109108001010000050201424131353360160000800105338153381533815338153381
800245338039900000123380000479462516001016001080010343813004950300533805338043290325134335280010800208002053380391180021109108001010000050201224111153360160000800105338153381533815338153381
800245338040000000112480000479462516001016001080010343813014950300533805338043290274934335280010800208002053380391180021109108001010000050201224141453360160000800105338153381533815338153381
80024533804000000014608000047946251600101600108001034381300495030053380533804329032513433528001080020800205338039118002110910800101000005020132471253360160000800105338153381533815338153381
80024533803990000011248000047946251600101600108001034381300495030053380533804329029363433528001080020800205338039118002110910800101000005020924121253360160000800105338153381533815338153381
800245338039900000116680000479462516001016001080010343813004950300533805338043290293634335280010800208002053380391180021109108001010000050201124141253360160000800105338153381533815338153381
800245338039900006110380000479462516001016001080010343813004950300533805338043290325134335280010800208002053380391180021109108001010000050201124131153360160000800105338153381533815338153381