Firestorm: STR (pre-index, 32-bit) measurements

Code:

  str w0, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	7	0	0	0	5	0	0	0	11	12	1025	17	1	0	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1020	0	55	2	14	1003	1	21	6	0	1016	0	31	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	4	22	1	0	16	0	1025	12	0	6	2	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1020	0	47	4	18	1001	0	28	12	0	1018	0	71	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	0	6	30	0	0	0	0	1025	0	3	2	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1018	0	40	0	18	1003	0	20	0	0	1018	0	39	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	4	14	1	0	8	0	1025	13	9	6	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1018	0	55	4	14	1000	0	16	12	0	1000	0	63	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	5	18	1	0	5	0	1025	12	2	0	2	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1015	0	63	5	14	1000	0	22	14	0	1008	0	95	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	1	0	4	0	0	0	0	0	1025	0	0	0	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1012	0	39	0	12	1003	0	14	6	0	1019	0	39	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	0	0	0	4	0	0	0	7	12	1025	13	2	4	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1020	0	79	2	20	1004	0	24	12	0	1015	0	63	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	5	18	1	0	0	12	1025	17	3	5	2	25	2000	1000	1000	1000	1000	50778	45824	1091	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1021	0	63	5	6	1008	0	24	0	3	1020	0	55	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	4	16	1	0	0	12	1025	13	0	0	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1000	0	55	0	0	1000	0	0	0	0	1000	0	71	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	0	0	0	5	22	1	0	7	0	1025	15	2	2	3	25	2000	1000	1000	1000	1000	50778	45824	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1018	0	46	5	20	1000	0	10	6	0	1020	0	55	73	1	16	1	1	1037	1000	1000	1000	1041	1092	1041	1041	1041

Test 2: Latency 2->2

Code:

  str w0, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10209	10040	75	0	0	0	2205	90	821	1	736	68	0	116	10025	817	57	98	62	25	20100	10100	10000	10106	10000	522071	468824	0	49	6960	10040	10040	8681	6	8742	20106	200	10008	200	20016	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10934	0	1424	401	0	637	10233	277	0	888	56	1032	10957	18	1245	7	0	1	1	1	718	0	16	0	0	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	2223	89	822	1	752	78	0	132	10025	774	66	88	49	25	20100	10100	10000	10106	10000	522079	468824	0	49	6960	10040	10040	8681	6	8742	20106	200	10008	200	20016	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10906	7	1297	376	0	677	10243	306	0	930	34	882	10944	18	1229	7	0	1	1	1	718	0	16	0	0	10037	10000	2	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	2337	98	824	1	744	72	0	120	10025	814	94	78	51	25	20100	10100	10000	10100	10000	522029	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10928	8	1344	373	0	666	10261	299	0	912	40	862	10922	19	1232	7	1	0	0	0	710	1	17	1	1	10037	10000	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	1	2256	83	828	1	752	76	0	120	10025	793	88	83	51	25	20100	10100	10000	10100	10000	522085	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10887	8	1375	393	0	695	10264	271	2	895	36	895	10952	21	1059	7	1	0	0	0	710	1	17	1	1	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	1	1	2229	80	824	1	712	80	0	164	10025	787	90	76	52	25	20100	10100	10000	10100	10000	522071	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10916	7	1322	396	0	698	10257	278	0	893	34	922	10912	19	1143	7	0	0	0	0	710	1	17	1	1	10037	10000	4	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	2334	89	818	1	752	61	0	168	10025	811	86	122	54	25	20100	10100	10000	10100	10000	522057	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10887	7	1264	410	0	681	10247	288	0	888	38	784	10896	18	1297	7	0	0	0	0	710	1	17	1	1	10037	10000	7	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	1	2463	85	824	1	704	83	0	152	10025	808	96	123	54	25	20100	10100	10000	10100	10000	522127	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10891	7	1308	397	0	675	10251	313	0	905	42	958	10915	25	1096	7	0	0	0	0	710	1	17	1	1	10037	10000	2	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	2304	89	824	1	776	70	0	116	10025	793	94	83	62	25	20100	10100	10000	10100	10000	522051	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10927	8	1185	400	0	671	10252	320	0	917	34	864	10938	20	1182	7	1	0	0	0	710	1	17	1	1	10037	10000	4	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	1	2262	93	792	1	736	82	0	112	10025	802	94	95	53	25	20100	10100	10000	10100	10000	522069	468824	0	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10938	16	1316	373	0	685	10271	283	0	920	42	974	10908	20	1297	7	1	0	0	0	710	1	17	1	1	10037	10000	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	1	0	0	2280	90	832	1	760	68	0	108	10025	786	56	94	49	25	20100	10100	10000	10100	10000	522131	468824	0	49	7113	10040	10090	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10913	8	1439	378	2	668	10251	294	0	885	34	906	10933	23	1209	7	1	0	0	0	710	1	17	1	1	10037	10000	4	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10029	10040	75	2169	77	828	1	768	77	1	120	10025	809	105	104	60	25	20010	10010	10000	10010	10000	521105	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10900	0	1306	358	722	10230	263	918	32	839	10904	11	1202	640	2	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2151	69	832	1	752	82	1	148	10025	792	104	88	57	25	20010	10010	10000	10010	10000	521089	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10922	0	1302	383	702	10236	291	922	36	892	10941	6	1226	640	3	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2184	76	770	1	768	80	5	96	10025	794	105	82	51	25	20010	10010	10000	10010	10000	521065	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10918	0	1342	367	704	10222	275	918	42	804	10997	8	1067	640	3	16	2	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2019	80	813	1	792	74	2	164	10025	804	127	118	53	25	20010	10010	10000	10010	10000	521081	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10890	0	1179	384	695	10234	274	906	40	820	10912	14	1176	640	3	16	3	3	10037	10000	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2214	88	804	1	808	64	1	96	10025	823	107	122	47	25	20010	10010	10000	10010	10000	521081	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10900	0	1340	406	708	10237	277	910	32	817	10941	15	1156	640	3	16	2	2	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2160	82	800	1	784	63	6	120	10025	760	111	97	54	25	20010	10010	10000	10010	10000	521129	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10904	0	1221	360	686	10246	270	902	32	828	10920	13	1082	640	2	16	2	2	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2016	83	814	1	808	65	4	120	10025	804	93	109	50	25	20010	10010	10000	10010	10000	521137	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10946	0	1321	379	695	10243	282	908	48	828	10947	11	1165	640	3	16	3	3	10037	10000	1	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2412	89	826	1	824	76	6	116	10025	803	93	66	51	25	20010	10010	10000	10010	10000	521097	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10898	0	1169	414	688	10232	264	916	40	839	10929	10	1177	640	2	16	3	2	10037	10000	3	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2040	76	820	1	776	95	3	116	10025	823	102	127	50	25	20010	10010	10000	10010	10000	521097	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10886	0	1200	387	685	10227	245	918	92	787	10916	12	1061	640	2	16	3	3	10037	10000	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2202	77	806	1	824	78	1	160	10025	805	96	84	51	25	20010	10010	10000	10010	10000	521129	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10898	0	1296	400	684	10218	270	938	36	716	10935	16	1149	640	2	16	3	3	10037	10000	3	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  str w0, [x6, #8]!
  str w0, [x7, #8]!
  str w0, [x8, #8]!
  str w0, [x9, #8]!
  str w0, [x10, #8]!
  str w0, [x11, #8]!
  str w0, [x12, #8]!
  str w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	40477	303	0	0	0	0	0	0	1893	500	833	1	728	97	96	40348	778	1985	2020	97	25	163990	80461	80000	80100	80000	403744	1860208	0	501	49	37334	40400	40526	30334	3	30326	160100	200	80000	200	160000	40514	75	1	1	80201	100	99	100	80000	100	80000	100	80912	0	4288	513	1	886	80301	272	0	926	44	1191	81227	240	3987	5110	3	17	3	2	40421	80830	80000	80100	40346	40392	40387	40499	40404
80204	40374	303	0	0	0	0	0	0	1977	368	809	1	672	110	120	40435	797	1802	1755	70	25	160628	83110	80000	80100	80000	402757	1859320	0	79	49	37352	40479	40470	30353	3	30336	160100	200	80000	200	160000	40461	75	1	1	80201	100	99	100	80000	100	80000	100	80901	0	4091	514	9	889	80224	278	0	929	74	1249	81134	228	4087	5110	2	17	3	3	40439	80438	80000	80100	40404	40451	40459	40403	40424
80204	40467	302	0	0	0	0	0	0	2172	378	802	1	696	89	100	40470	790	1803	1929	105	25	160661	82538	80019	80212	80000	401540	1859776	0	390	49	37368	40394	40377	30405	3	30421	160100	200	80000	200	160000	40353	82	1	1	80201	100	99	100	80000	100	80000	100	80902	0	4510	509	10	881	80260	251	0	904	78	1132	81123	250	4406	5110	2	16	3	3	40343	82169	80000	80100	40451	40364	40401	40389	40411
80204	40415	303	0	0	0	0	0	0	2070	345	793	1	688	111	108	40388	764	1829	2008	80	25	161639	85421	80006	80100	80000	412014	1856944	0	386	49	37483	40457	40384	30441	3	30368	160100	200	80000	200	160000	40476	75	1	1	80201	100	99	100	80000	100	80000	100	80838	0	4552	522	10	862	80243	261	0	912	34	1201	81135	245	4287	5110	3	16	3	3	40405	80276	80000	80100	40403	40427	40473	40422	40359
80204	40462	302	0	0	0	0	2	0	2136	362	837	1	728	108	100	40407	797	1969	1910	117	25	163774	82890	80017	80100	80000	402437	1857520	0	1781	49	37325	40449	40393	30377	3	30356	160100	200	80000	200	160000	40353	75	1	1	80201	100	99	100	80000	100	80000	100	80916	0	4113	507	9	871	80246	308	0	887	44	1061	81146	247	4312	5110	3	16	3	2	40444	83806	80000	80100	40405	40347	40401	40435	40434
80204	40364	302	0	0	0	0	0	0	2010	336	822	1	720	95	92	40454	770	1789	1797	128	25	161405	80524	80000	80100	80000	402580	1858768	0	54	49	37428	40378	40391	30309	3	30317	160100	200	80000	200	160000	40548	75	1	1	80201	100	99	100	80000	100	80000	100	80932	0	4300	548	4	880	80246	290	0	918	40	1135	81074	268	4259	5110	3	16	3	3	40427	80975	80000	80100	40362	40480	40405	40386	40428
80204	40435	304	0	0	0	0	0	0	2118	388	819	1	672	110	112	40447	799	1814	1965	86	25	162745	80659	80000	80100	80000	402542	1857592	0	2337	49	37323	40405	40420	30267	3	30353	160100	200	80000	200	160000	40430	75	1	1	80201	100	99	100	80000	100	80000	100	80910	0	3904	511	11	888	80278	285	0	876	34	1234	81090	237	4124	5110	3	17	3	3	40381	80454	80000	80100	40407	40383	40406	40428	40389
80204	40480	303	0	0	0	0	0	0	2055	313	802	1	696	92	112	40443	788	2113	1962	74	25	164102	82934	80000	80100	80000	404590	1853896	0	402	49	37327	40453	40397	30295	3	30332	160100	200	80000	200	160000	40366	75	1	1	80201	100	99	100	80000	100	80000	100	80900	0	4479	572	12	847	80263	306	0	906	46	1127	81134	237	4531	5110	3	17	3	3	40459	80147	80000	80100	40477	40459	40412	40347	40381
80204	40401	303	0	0	0	0	0	0	1854	379	815	1	416	116	136	40337	775	1826	1844	89	25	160475	83093	80000	80100	80000	402235	1858504	0	249	49	37289	40371	40431	30273	3	30427	160100	200	80000	200	160000	40389	82	1	1	80201	100	99	100	80000	100	80000	100	80860	0	4503	536	7	911	80242	278	0	877	50	1190	81157	234	4010	5110	3	16	3	3	40429	80280	80000	80100	40355	40422	40365	40435	40386
80204	40431	302	0	0	0	0	0	0	1989	348	805	1	760	91	140	40437	790	1986	1930	91	25	160424	83293	80000	80100	80000	401726	1857592	1	257	49	37339	40374	40395	30369	3	30372	160100	200	80000	200	160000	40528	82	1	1	80201	100	99	100	80000	100	80000	100	80913	0	4414	520	5	884	80246	260	0	885	44	1155	81118	248	4379	5110	3	16	3	3	40530	80495	80000	80100	40513	40440	40388	40372	40425

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5098

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	c3	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	40632	306	2	2	2	0	0	0	1872	926	771	1	760	115	140	40809	776	1606	1866	136	25	160384	80495	80132	80010	80000	410681	1875880	0	1	265	49	37732	40801	40768	30638	3	30773	160010	20	80000	20	160000	40850	75	1	1	80021	10	9	10	80000	10	80000	10	80922	27	3622	439	3	811	80478	251	4	886	46	1666	81359	514	3865	26	0	0	5020	0	0	0	4	17	0	4	6	40804	80501	0	80000	80010	40818	40801	40796	40780	40753
80024	40751	306	3	3	3	0	0	0	1890	854	795	1	656	124	140	40787	742	1597	1721	141	25	160220	83065	80000	80010	80000	401834	1875496	1	1	1812	49	37730	40754	40873	30681	3	30760	160010	20	80000	20	160000	40819	75	1	1	80021	10	9	10	80000	10	80000	10	80905	28	3644	463	1	829	80528	232	0	840	44	1767	81436	561	3969	27	0	0	5020	0	0	0	6	16	0	4	4	40814	83404	0	80000	80010	40827	40735	40830	40775	40825
80024	40914	318	2	0	0	0	0	0	1869	888	737	1	712	110	120	40784	782	2089	1763	165	25	160630	80433	80000	80010	80000	401596	1871344	0	1	206	49	37648	40796	40810	30670	3	30802	160010	20	80000	20	160000	40894	82	1	1	80021	10	9	10	80000	10	80000	10	80900	26	3965	478	8	857	80569	286	0	848	32	1740	81309	546	3622	24	0	0	5020	3	0	0	7	16	0	4	4	40854	80382	0	80000	80010	40804	40772	40780	40808	40810
80024	40786	306	3	3	0	0	0	0	2043	890	770	1	728	128	108	40872	759	1766	1791	190	25	160457	80712	80014	80010	80000	402278	1875736	0	1	1197	49	37727	40842	40711	30827	3	30823	160010	20	80000	20	160000	40817	82	1	1	80021	10	9	10	80000	10	80000	10	80905	20	3907	463	6	881	80498	267	0	873	34	1568	81432	550	3705	27	0	0	5022	0	0	0	8	17	0	4	4	40839	80455	0	80000	80010	40815	40765	40867	40820	40815
80024	40756	305	3	3	0	0	0	0	1995	887	822	1	656	100	128	40778	779	1718	1825	131	25	160644	82635	80000	80010	80000	401090	1877920	0	1	356	49	37675	40845	40837	30826	3	30783	160010	20	80000	20	160000	40789	75	1	1	80021	10	9	10	80000	10	80000	10	80943	25	3645	503	5	832	80516	275	3	881	30	1655	81370	529	4021	35	3	0	5020	0	0	0	4	16	0	4	4	40799	80428	0	80000	80010	40799	40821	40878	40800	40789
80024	40775	306	3	0	0	3	0	0	1911	900	779	1	664	135	108	40781	785	1860	1847	149	25	160516	80353	80000	80010	80000	402039	1876936	0	1	2940	49	37748	40806	40715	30745	3	30817	160010	20	80000	20	160000	40730	75	1	1	80021	10	9	10	80000	10	80000	10	80928	28	3656	496	10	867	80539	259	0	857	28	1698	81355	502	3240	12	2	0	5020	0	0	0	4	16	0	6	9	40859	80589	0	80000	80010	40859	40907	40766	40814	40835
80024	40747	305	2	0	2	2	0	0	1773	827	815	1	720	114	116	40768	809	1544	1723	171	25	160633	85987	80060	80010	80000	402022	1877992	0	1	292	49	37680	41267	40854	30764	3	30658	160010	20	80000	20	160000	40739	75	1	1	80021	10	9	10	80000	10	80000	10	80889	28	4354	473	8	876	80551	298	0	875	40	1504	81397	461	3852	27	0	0	5020	0	0	0	4	16	0	3	8	40806	80605	0	80000	80010	40718	40846	40701	40771	40828
80024	40836	306	2	0	0	0	0	0	1974	822	768	1	696	126	132	40886	766	1892	1855	138	25	164856	80679	80213	80010	80000	401502	1891816	0	1	434	49	37710	40768	40732	30741	3	30701	160010	20	80000	20	160000	40807	75	1	1	80021	10	9	10	80000	10	80000	10	80910	21	4265	415	11	865	80557	258	0	888	40	1595	81326	554	3969	24	2	0	5020	3	0	0	4	16	0	8	6	40785	85875	0	80000	80010	40798	40738	40767	40722	40788
80024	40730	306	2	0	0	0	0	0	1899	737	772	1	680	128	136	40765	784	1706	1686	192	25	162395	80424	80000	80010	80000	402198	1878208	0	1	250	49	37759	40769	40928	30797	3	30749	160010	20	80000	20	160000	40736	82	1	1	80021	10	9	10	80000	10	80000	10	80890	27	3925	481	9	814	80536	258	0	815	44	1612	81340	533	4058	27	0	0	5020	0	0	0	7	17	0	4	3	40764	83069	0	80000	80010	40784	40873	40788	40799	40757
80024	40824	306	2	0	2	0	0	0	1641	855	788	1	704	107	104	40746	748	1652	1765	156	25	164664	80718	80011	80010	80000	401703	1876000	0	1	343	49	37728	40751	40748	30774	3	30817	160010	20	80000	20	160000	40785	82	1	1	80021	10	9	10	80000	10	80000	10	80925	43	4389	430	12	865	80521	281	0	901	42	1674	81342	535	4235	39	3	0	5056	0	0	0	7	16	0	4	3	40847	80434	0	80000	80010	40831	40827	41295	40800	40811

STR (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations