Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (immediate, 64-bit)

Test 1: uops

Code:

  adds x0, x0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10041035861917251000100010006225011035103580538821000100010001035401110011000073227119931000100010361036103610361036
10041035761917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035861917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035861917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035771917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035761917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035761917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035761917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035861917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036
10041035784917251000100010006225001035103580538821000100010001035401110011000073127119931000100010361036103610361036

Test 2: Latency 1->2

Code:

  adds x0, x0, #3
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071012711999510000101001003610036100361003610036
1020410035750102619920251010010100101006471520496955100351003586563873210100102001020010035401110201100991001010010031371012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471520496955100351003586563873210100102001020010035401110201100991001010010006371012711999510000101001003610036100361003610036
1020410035750094992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071012711999510000101001003610036100361003610036
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000074812711999510000101001003610036100361003610036
102041003575106199202510100101001010064715204969551003510035865638732101001020010200100354011102011009910010100100081871012711999510000101001003610036100361003610036
1020410035750061992025101001010010100647152049695510035100358656387321010010200102001003540111020110099100101001000071012711999510000101001003610036100361003610036
102041003575006199202510100101001010064715214969551003510035865638732101001020010200100354011102011009910010100100010271012711999510000101001003610036100361003610036
10204100357500619920251010010100101006471521496955100351003586563873210100102001020010035401110201100991001010010024371012711999510000101001003610036100361003610036
1020410035750061992025101001010010100647152149695510035100358656387321010010200102001003540111020110099100101001000071012711999510000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101040064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101010064022722999710000100101003610036100361003610036
1002410035753619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010054064022722999710000100101003610036100361003610036
1002410035751261991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101020064022722999710000100101003610036100361003610036
100241003575361991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101003064022722999710000100101003610036100361003610036
1002410035750619918251001010010100106472460496955100351003586783875410010100201002010035401110021109101001010326064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036
100241003575061991825100101001010010647246049695510035100358678387541001010020100201003540111002110910100101000064022722999710000100101003610036100361003610036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  adds x0, x1, #3
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500611993025201002010020112129723314916955200352003517425817486201122022420224200356411202011009910020100101001001111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425817485201122022420224200356411202011009910020100101000001111320162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425817486201122022420224200356411202011009910020100101000001111319162001220000201002003620036200362003620036
202042003515006119930252010020100201121297233149169552003520035174258174852011220224202242003564112020110099100201001010014003111319162001220000201002003620036200362003620036
20204200351506611993025201002010020112129723304916955200352003517425817485201122022420224200356411202011009910020100101001031111320162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955200352003517425717485201122022420224200356411202011009910020100101000031111320162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425817485201122022420224200356411202011009910020100101000001111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955200352003517425717486201122022420224200356411202011009910020100101000031111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723314916955200352003517425717486201122022420224200356411202011009910020100101001031111319162001220000201002003620036200362003620036
20204200351500611993025201002010020112129723304916955200352003517425717486201122022420224200356411202011009910020100101000031111319162001220000201002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03l1d tlb fill (05)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010001270227321999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010421771270327221999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035642120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010001270227221999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010001270327221999520000200102003620036200362003620036
20024200351501061199182520010200102001012972474916955200352003517428317504200102002020020200356411200211091020010100102601270227231999520000200102003620036200362003620036
2002420035150006119918252001020010200101297247491695520035200351742831750420010200202002020035641120021109102001010010001270227221999520000200102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  adds x0, x8, #3
  adds x1, x8, #3
  adds x2, x8, #3
  adds x3, x8, #3
  adds x4, x8, #3
  adds x5, x8, #3
  adds x6, x8, #3
  adds x7, x8, #3
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426752201002829801158011580121400590149236612674126741166798166898012180232802322674139118020110099100801001000000001115120016002673880000801002673626736267362673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000000005110119112673180000801002673626736267362673626736
80204267352000012325801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000100005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000000005110119112673180000801002673626736267362673626736
80204267352010035258010080100801004005000492365526735267351667231669080100802008020026735391180201100991008010010000012730005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000000005110119112673180000801002673626736267362673626736
80204267352010022525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000000005110119112673180000801002673626736267362673626736
8020426735201003525801008010080100400500149236552673526735166723166908010080200802002673539118020110099100801001000000000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000000000005110119112673180000801002673626736267362673626736
8020426735200003525801008010080100400500049236552673526735166723166908010080200802002673539118020110099100801001000030130005110119112673180000801002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03l1i tlb fill (04)191e3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
800242671120000025225800108001080010400050149236252670526705166650316683800108002080020267053911800211091080010100005022151814112670280000019800102670626706267062670626706
800242670520010015225800108001080010400050049236252670526705166650316683800108002080020267053911800211091080010100005022151813112670280000042800102670626706267062670626706
800242670520010015225800108001080010400050049236252670526705166650316683800108002080020267053911800211091080010100005022141810132670280000047800102670626706267062670626706
80024267052001001522580010800108001040005014923625267052670516665031668380010800208002026705391180021109108001010000502291817162670280000029800102670626706267062670626706
800242670520010015225800108001080010400050149236252670526705166650316683800108002080020267053911800211091080010100005022151813142670280000030800102670626706267062670626706
80024267052001001522580010800108001040005014923625267052670516665031668380010800208002026705391180021109108001010000502210189132670280000030800102670626706267062670626706
8002426705200100152725800108001080010400050049236252670526705166650316683800108002080020267053911800211091080010100005022111813152670280000048800102670626706267062670626706
800242670520010015225800108001080010400050149236252670526705166650316683800108002080020267058311800211091080010100005022141813172670280000040800102670626706267062670626706
800242670520010015225800108001080010400050149236252670526705166650316683800108002080020267053911800211091080010100005024171814152670280000029800102670626706267062670626706
800242670520010015225800108001080010400050149236252670526705166650316683800108002080020267053911800211091080010100005022131815132670280000040800102670626706267062670626706