Firestorm: LDRSH (register, lsl, 64-bit) measurements

Code:

  ldrsh x0, [x6, x7, lsl #1]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	45	0	0	1	379	2	0	0	2	25	1000	1000	1000	15037	1	374	394	217	3	252	1000	1000	2000	374	56	1	1	1001	1000	1000	0	1000	39	1039	0	39	1035	6	1	0	39	73	1	16	1	1	391	6	6	2	1000	390	395	375	390	395
1004	394	3	0	0	41	0	0	0	374	0	12	12	12	25	1000	1000	1000	14838	0	394	394	217	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	1039	0	39	1039	6	1	35	43	73	1	16	1	1	386	10	0	0	1000	394	390	393	375	395
1004	374	2	0	1	45	0	0	2	374	2	12	0	0	25	1000	1000	1000	15018	1	374	394	216	3	252	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	39	1039	0	35	1035	6	1	39	43	73	1	16	1	1	386	6	6	4	1000	378	390	395	395	396
1004	394	3	1	1	45	0	0	1	359	2	18	0	16	25	1000	1000	1000	14060	1	394	394	197	3	247	1000	1000	2000	394	72	1	1	1001	1000	1000	0	1000	0	1035	0	35	1039	0	1	0	43	73	1	16	1	1	386	0	6	0	1000	395	375	395	375	375
1004	374	3	0	1	0	0	0	0	359	2	12	0	0	25	1000	1000	1000	15207	1	389	374	217	3	233	1000	1000	2000	374	71	1	1	1001	1000	1000	0	1000	39	1000	0	42	1039	0	0	39	43	73	1	16	1	1	371	10	0	4	1000	375	375	379	395	395
1004	374	3	0	0	0	0	0	0	374	2	0	12	1	25	1000	1000	1000	14989	0	374	374	217	3	247	1000	1000	2000	389	56	1	1	1001	1000	1000	0	1000	39	1039	0	0	1033	6	1	35	0	73	1	16	1	1	386	0	6	4	1000	375	395	395	395	390
1004	391	3	0	0	0	1	0	2	374	2	18	0	0	25	1000	1000	1000	14060	1	374	394	217	3	232	1000	1000	2000	389	72	1	1	1001	1000	1000	0	1000	39	1000	1	39	1035	6	1	35	43	73	1	16	1	1	391	0	0	4	1000	390	397	395	395	375
1004	394	3	1	1	45	0	0	0	374	2	18	18	12	25	1000	1000	1000	14838	1	394	394	217	3	232	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	1039	0	0	1035	6	1	35	0	73	1	16	1	1	371	10	0	4	1000	375	375	395	395	375
1004	389	3	0	0	42	1	0	2	379	2	0	0	12	25	1000	1000	1000	14989	0	374	374	217	3	247	1000	1000	2000	374	56	1	1	1001	1000	1000	0	1000	0	1000	2	51	1039	6	1	0	0	73	1	16	1	1	388	10	0	0	1000	375	375	375	375	390
1004	394	3	1	0	45	1	0	1	380	0	15	12	0	25	1000	1000	1000	14838	1	374	394	217	3	247	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	39	1035	0	35	1035	6	0	0	0	73	1	16	1	1	391	0	6	2	1000	398	377	379	375	375

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	0	0	0	0	1	2	1	0	1	70042	69702	59718	25	40108	30106	10002	30100	10000	616068	3341769	1	49	66977	0	70036	70054	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	1	10000	1	0	1	1	1	0	2610	1	71	1	1	69820	30003	10	10	0	10000	30100	70058	70042	70058	70058	70058
40204	70057	525	1	1	0	0	0	1	0	0	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616014	3341470	1	49	66971	0	70090	70053	64650	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	0	0	0	1	0	0	2610	1	71	1	1	69798	30003	10	10	10	10000	30100	70153	70036	70052	70036	70052
40204	70035	525	0	0	0	0	0	6	0	0	0	70036	69782	59695	25	40104	30100	10001	30100	10000	616175	3342254	1	49	66974	0	70112	70088	64647	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70035	525	0	0	0	1	1	0	1	0	0	70020	69782	59710	25	40104	30103	10001	30100	10000	616175	3342254	1	49	66971	0	70089	70051	64647	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	3	10000	0	0	1	0	0	0	2610	1	71	1	1	69814	30003	0	10	0	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	1	0	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	0	70104	70055	64648	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10001	0	0	2	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69820	30006	10	0	10	10000	30100	70058	70042	70061	70042	70058
40204	70060	524	1	0	1	0	0	1	1	0	0	70036	69764	59695	25	40104	30103	10000	30100	10000	616014	3342254	1	49	66971	0	70071	70056	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70036	70052	70052	70036	70052
40204	70051	524	0	0	0	0	1	0	0	0	0	70036	69782	59710	25	40104	30100	10001	30100	10000	616014	3342398	1	49	66971	0	70091	70056	64647	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	4	0	2610	1	71	1	1	69798	30003	10	10	10	10000	30100	70052	70052	70036	70052	70052
40204	70051	525	0	0	0	0	0	0	1	0	0	70036	69764	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66955	0	70107	70054	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	0	0	10	10000	30100	70036	70052	70036	70036	70052
40204	70051	524	0	0	0	0	0	2	1	0	1	70042	69788	59716	25	40108	30103	10002	30100	10000	616068	3341769	1	49	66977	0	70086	70058	64653	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	1	0	0	1	10000	1	1	0	1	3	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70061	70058	70042	70058	70058
40204	70041	524	1	1	0	0	0	2	0	0	0	70042	69788	59716	25	40104	30106	10002	30100	10000	616068	3342542	1	49	66971	0	70088	70053	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	0	10000	0	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	0	10000	30100	70052	70036	70036	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	1	1	1	0	1	0	0	2	1	0	1	70041	69777	59715	25	40018	30013	10002	30010	10000	616995	3342494	1	49	66995	70053	70053	64671	3	64966	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	1	1	10000	1	1	1	1	2	2520	3	71	2	3	69816	30006	6	0	6	10000	30010	70042	70042	70054	70054	70054
40024	70053	525	1	0	0	0	1	1	0	2	1	0	0	70026	69777	59712	25	40018	30016	10002	30010	10000	617009	3342350	0	49	66973	70041	70041	64671	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	0	10001	0	0	1	10006	1	1	0	1	0	2520	2	71	2	3	69824	30006	6	6	0	10000	30010	70054	70054	70042	70042	70057
40024	70041	524	1	0	0	1	0	0	0	7	0	0	1	70248	69777	59712	25	40018	30016	10002	30010	10000	617009	3341769	0	49	66973	70053	70053	64659	3	64978	40010	30020	10000	60020	20000	70064	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	2	1	1	10000	0	1	1	1	0	2520	2	71	4	4	69804	30006	9	0	6	10000	30010	70054	70054	70054	70042	70042
40024	70041	524	1	0	0	1	0	0	0	2	0	0	0	70038	69777	59715	25	40018	30013	10002	30010	10000	617009	3342350	0	49	66982	70053	70041	64671	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10001	0	1	1	10000	1	1	1	1	0	2520	3	71	4	2	69804	30006	6	6	0	10000	30010	70054	70054	70054	70042	70054
40024	70053	524	1	1	0	0	0	0	0	2	0	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	617036	3342494	1	49	66995	70041	70056	64671	3	64981	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	1	1	10000	1	1	0	1	1	2520	3	71	2	3	69816	30006	6	6	6	10000	30010	70054	70054	70057	70042	70042
40024	70056	525	1	0	1	0	0	0	0	1	0	0	1	70038	69777	59712	25	40018	30016	10002	30010	10000	616995	3341769	0	49	66975	70056	70053	64659	3	64978	40010	30020	10000	60020	20000	70053	77	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	1	1	1	10000	1	1	0	1	0	2520	2	71	4	2	69804	30006	0	6	6	10000	30010	70054	70042	70054	70054	70057
40024	70053	525	1	1	0	1	0	0	0	1	1	0	0	70026	69777	59712	25	40018	30013	10002	30010	10000	617009	3342350	0	49	67027	70041	70056	64671	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	0	10001	0	1	1	10000	0	1	1	1	0	2520	2	71	2	2	69804	30006	0	0	0	10000	30010	70054	70054	70054	70042	70057
40024	70041	525	1	1	0	0	0	0	3	2	0	0	1	70041	69780	59712	25	40018	30016	10002	30010	10000	617009	3342350	1	49	67012	70041	70053	64671	3	64966	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10002	0	2	1	10000	0	1	1	1	1	2520	4	71	3	3	69804	30006	6	6	0	10000	30010	70054	70054	70042	70057	70054
40024	70056	524	1	1	1	1	0	0	0	2	0	0	1	70041	69777	59715	25	40018	30016	10002	30010	10000	617009	3341769	0	49	67040	70053	70053	64674	3	64978	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	1	10000	0	1	1	1	0	2520	4	71	3	5	69816	30006	6	0	6	10000	30010	70054	70054	70042	70054	70042
40024	70053	524	1	1	0	1	0	0	0	2	1	0	1	70026	69702	59712	25	40014	30016	10001	30010	10000	616995	3341769	0	49	66973	70053	70053	64659	3	64979	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	0	1	10000	1	1	1	1	0	2520	2	71	4	2	69816	30006	6	0	6	10000	30010	70054	70042	70054	70054	70042

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	524	0	0	1	0	0	0	2	1	0	70045	69791	59719	25	40108	30103	10002	30100	10000	616078	3342686	0	49	66983	0	70060	70041	64656	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	0	10002	0	0	0	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30006	0	10	13	10000	30100	70042	70061	70042	70058	70061
40204	70060	524	1	1	0	2	1	1	1	0	0	70045	69702	59719	25	40153	30106	10002	30100	10000	616095	3342830	0	49	67016	0	70060	70060	64656	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	0	0	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69823	30006	13	0	13	10000	30100	70042	70061	70061	70061	70061
40204	70041	543	1	1	0	1	0	0	2	0	0	70045	69791	59719	25	40108	30106	10002	30100	10000	616078	3342686	1	49	66982	0	70060	70060	64656	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10003	0	0	0	1	10000	1	1	0	1	2	0	2610	1	71	1	1	69804	30006	13	13	13	10000	30100	70042	70061	70061	70042	70061
40204	70041	524	1	0	0	1	0	0	2	0	0	70045	69791	59719	25	40120	30103	10002	30100	10000	616078	3342542	0	49	66980	0	70060	70060	64656	3	64944	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10002	0	0	2	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69823	30006	13	13	13	10000	30100	70061	70061	70042	70062	70061
40204	70041	524	1	1	0	0	0	0	2	0	1	70045	69791	59719	25	40108	30106	10002	30100	10000	616068	3342686	1	49	66982	0	70041	70060	64656	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	0	0	4	10000	1	1	1	1	1	0	2610	1	71	1	1	69804	30003	10	10	0	10000	30100	70061	70042	70042	70058	70042
40204	70060	524	1	0	0	1	0	0	10	1	1	70042	69788	59701	25	40108	30103	10002	30100	10000	616095	3342686	1	49	66978	0	70057	70041	64653	3	64960	40100	30200	10000	60200	20000	70062	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	2	1	10002	0	0	0	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69823	30006	13	10	13	10000	30100	70042	70061	70061	70042	70042
40204	70060	525	1	1	0	0	0	0	2	1	0	70026	69791	59719	25	40108	30106	10002	30100	10000	616095	3341769	1	49	66978	0	70041	70060	64656	3	64973	40100	30200	10000	60200	20000	70041	35	1	1	40202	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	0	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69820	30003	13	0	13	10000	30100	70061	70042	70061	70042	70042
40204	70060	525	1	0	0	1	0	0	1	1	0	70045	69788	59716	25	40104	30103	10002	30100	10000	616068	3341769	1	49	66967	0	70042	70060	64637	3	64944	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10001	0	0	0	1	10000	1	1	0	1	1	0	2610	1	71	1	1	69804	30003	10	13	0	10000	30100	70042	70061	70061	70061	70061
40204	70060	524	1	1	0	1	0	0	1	0	0	70045	69791	59716	25	40108	30103	10002	30100	10000	616078	3342686	1	49	66977	0	70057	70057	64653	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	2	1	10002	0	0	0	1	10000	1	1	0	1	0	0	2610	1	71	1	1	69804	30006	0	13	13	10000	30100	70061	70061	70061	70042	70061
40204	70041	525	1	1	0	1	0	0	1	0	0	70045	69788	59701	25	40104	30103	10001	30100	10000	616078	3342542	0	49	66963	0	70060	70060	64656	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	2	0	10001	0	1	0	4	10000	1	1	1	1	1	0	2610	1	71	1	1	69804	30006	13	0	0	10000	30100	70055	70061	70061	70061	70061

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	524	0	0	0	1	0	1	0	70036	69775	59710	25	40020	30013	10002	30010	10000	616991	3342254	0	49	66971	70051	70051	64653	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	77	0	18	10000	1	1	1	0	0	2522	0	2	71	2	2	69814	30005	10	10	10	10000	30010	70036	70052	70052	70052	70142
40024	70057	525	0	0	0	1	0	1	0	70020	69775	59710	25	40016	30013	10001	30010	10000	616991	3342890	0	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	51	0	0	10000	1	1	0	0	0	2520	0	2	71	2	2	69814	30003	0	10	10	10000	30010	70052	70052	70052	70052	70141
40024	70035	525	0	0	0	0	0	0	0	70036	69775	59695	25	40014	30013	10001	30012	10000	616991	3342254	0	49	66955	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	77	0	0	10000	0	0	0	0	0	2520	0	2	71	2	2	69814	30003	10	10	10	10000	30010	70052	70036	70052	70052	70052
40024	70052	525	0	0	0	1	0	1	0	70036	69775	59695	25	40014	30013	10000	30010	10000	616991	3341470	0	49	66955	70051	70051	64672	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	82	0	0	10000	1	1	0	0	0	2520	0	2	71	2	2	69814	30003	10	10	10	10000	30010	70052	70052	70052	70036	70055
40024	70090	525	0	0	0	0	0	0	0	70036	69775	59710	25	40014	30013	10001	30012	10000	617068	3342254	0	49	66971	70051	70051	64653	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	74	0	0	10000	1	1	0	0	0	2520	0	2	71	2	2	69814	30003	10	10	10	10000	30010	70052	70052	70052	70052	70119
40024	70051	524	0	0	0	1	0	1	0	70036	69757	59710	25	40014	30015	10001	30012	10000	616991	3342254	0	49	66971	70051	70051	64669	3	64977	40012	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	74	0	0	10000	1	0	0	0	0	2520	0	2	71	2	3	69814	30003	10	10	10	10000	30010	70052	70052	70052	70052	70133
40024	70052	524	0	0	0	1	0	1	0	70020	69775	59710	25	40014	30010	10001	30010	10000	616991	3342254	0	49	66971	70051	70051	64653	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	72	0	0	10000	0	0	0	0	0	2522	0	3	71	2	2	69814	30003	10	10	10	10000	30010	70052	70036	70052	70052	70137
40024	70051	524	0	0	0	1	0	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	75	0	0	10000	0	0	0	0	0	2522	0	2	71	2	4	69814	30003	10	10	10	10000	30010	70052	70052	70052	70053	70036
40024	70054	525	0	0	0	1	0	0	0	70036	69743	59710	25	40014	30013	10000	30010	10000	616991	3342254	0	49	66971	70051	70051	64671	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	8	0	0	10000	1	1	0	0	0	2520	0	2	71	2	2	69814	30000	10	10	10	10000	30010	70054	70054	70052	70053	70073
40024	70053	525	0	0	1	265	176	1	0	70038	69901	59710	50	40016	30035	10001	30443	10051	619161	3342254	1	49	66971	70051	70051	64672	3	64960	40010	30020	10000	60020	20000	70036	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	54	0	0	10003	1	1	0	0	0	2522	0	2	71	4	3	69820	30003	10	10	10	10000	30010	70055	70054	70052	70055	70052

Test 4: throughput

Count: 8

Code:

  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	1	1	1	78	0	2	26707	2	18	18	12	25	80100	100	80000	100	80014	500	1166596	0	49	23645	26733	26730	16650	6	16674	80114	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	0	80039	0	42	80000	6	1	35	39	0	1	1	1	5118	2	16	2	2	26704	0	0	0	0	80000	100	26708	26723	26728	26723	26708
80204	26722	200	0	1	0	45	1	1	26707	0	18	18	0	25	80100	100	80000	100	80015	500	1165856	0	49	23633	26729	26722	16653	6	16659	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80039	0	0	80000	6	1	35	39	0	1	1	1	5118	2	16	2	2	26719	0	10	0	4	80000	100	26723	26728	26723	26708	26708
80204	26707	200	1	0	0	0	0	0	26692	2	18	18	11	25	80100	100	80000	100	80016	500	1167875	0	49	23653	26737	26722	16635	6	16679	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	0	80039	0	35	80039	6	0	39	43	0	1	1	1	5118	1	16	2	2	26719	0	6	0	4	80000	100	26728	26708	26723	26728	26723
80204	26722	200	0	0	0	41	1	0	26713	2	12	0	16	25	80100	100	80000	100	80015	500	1167303	0	49	23633	26716	26728	16650	6	16674	80115	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80039	0	39	80000	0	1	0	0	4	1	1	1	5118	2	16	2	2	26724	0	10	6	4	80000	100	26728	26728	26723	26708	26723
80204	26722	200	0	0	0	0	1	1	26707	0	0	0	12	25	80100	100	80000	100	80014	500	1166596	0	49	23648	26720	26728	16658	6	16674	80115	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	0	80039	0	38	80035	6	1	39	39	0	1	1	1	5118	1	16	1	2	26719	0	6	10	4	80000	100	26728	26728	26723	26728	26723
80204	26722	200	0	0	0	41	0	2	26707	2	18	18	16	25	80100	100	80000	100	80014	500	1167875	0	49	23649	26736	26731	16650	6	16674	80114	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	100	80000	43	0	80039	0	39	80035	6	1	2	39	0	1	1	1	5118	2	16	2	1	26704	0	0	6	2	80000	100	26708	26723	26728	26723	26728
80204	26727	200	1	0	0	0	1	1	26712	2	0	12	0	25	80100	100	80000	100	80015	500	1167875	1	49	23642	26847	26743	16823	6	16674	80114	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	100	80000	39	0	80000	0	38	80000	6	1	35	39	0	1	1	1	5118	1	16	1	2	26719	0	0	6	2	80000	100	26723	26723	26723	26708	26708
80204	26722	200	0	0	0	41	0	1	26707	2	0	18	0	25	80100	100	80000	100	80015	500	1167875	0	49	23647	26735	26722	16650	6	16679	80114	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	100	80000	39	0	80039	0	39	80040	0	1	0	0	0	1	1	1	5118	2	16	2	2	26704	0	6	10	2	80000	100	26708	26728	26708	26723	26728
80204	26722	200	0	0	0	41	0	1	26707	0	0	12	12	25	80100	100	80000	100	80015	500	1166596	1	49	23634	26715	26725	16650	6	16659	80115	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	100	80000	39	0	80035	0	35	80039	6	1	35	0	0	1	1	1	5118	1	16	1	2	26719	0	10	6	2	80000	100	26723	26708	26723	26708	26728
80204	26730	200	0	0	0	53	1	1	26707	2	0	0	16	25	80100	100	80000	100	80016	500	1167303	1	49	23656	26736	26731	16635	6	16659	80114	200	80024	200	160048	26722	72	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80000	0	35	80000	6	1	35	43	0	1	1	1	5118	2	16	1	2	26704	0	0	10	4	80000	100	26728	26728	26708	26723	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d0	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26737	200	1	1	0	0	1	0	0	67	0	3	26722	3	7	7	3	25	80010	10	80000	10	80000	50	1168472	0	1	0	49	23657	26736	26715	16681	3	16717	80010	20	80000	20	160000	26737	86	1	1	80021	10	9	0	10	80000	10	80000	0	10	80020	19	44	80019	1	0	0	60	80041	6	1	58	44	19	0	0	5021	0	1	17	16	16	17	26711	117	13	0	80000	10	26745	26740	26752	26737	26716
80024	26737	201	1	1	1	1	0	1	0	73	0	2	26722	2	0	7	20	25	80010	10	80000	10	80000	50	1167219	0	1	0	49	23657	26736	26736	16660	3	16717	80010	20	80000	20	160000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	19	43	80059	1	0	0	61	80040	6	1	58	43	19	2	0	5021	0	1	14	16	10	17	26734	103	0	5	80000	10	26715	26737	26737	26737	26738
80024	26737	200	1	1	0	2	0	0	0	21	0	2	26722	3	7	7	19	25	80010	10	80000	10	80000	50	1173975	0	1	0	49	23656	26736	26736	16681	3	16694	80010	20	80000	20	160000	26714	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	0	80019	1	0	1	61	80039	6	0	19	43	19	2	0	5021	0	1	15	16	17	14	26733	103	13	5	80000	10	26739	26737	26737	26716	26737
80024	26737	200	1	1	1	1	1	0	0	67	0	3	26721	0	7	7	20	25	80010	10	80000	10	80000	50	1167219	0	1	0	49	23656	26736	26736	16682	3	16717	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	44	80059	0	0	1	60	80041	6	1	59	43	19	0	0	5021	0	1	16	16	17	16	26734	103	13	5	80000	10	26739	26737	26738	26738	26737
80024	26736	200	1	1	1	2	0	0	0	66	0	0	26699	3	0	0	19	25	80010	10	80000	10	80000	50	1173975	0	1	0	49	23635	26715	26736	16681	3	16716	80010	20	80000	20	160000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	80019	0	0	1	61	80040	6	1	19	0	19	0	0	5021	0	1	10	16	17	10	26733	117	13	5	80000	10	26738	26744	26842	26738	26738
80024	26715	200	1	1	0	2	1	0	0	66	0	2	26700	3	7	7	2	25	80010	10	80000	10	80000	50	1166522	0	1	0	49	23657	26715	26737	16681	3	16717	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80020	19	43	80062	0	0	0	21	80000	0	1	59	43	19	0	0	5021	3	1	17	16	14	17	26711	114	13	5	80000	10	26716	26738	26715	26738	26716
80024	26736	201	1	1	1	2	0	0	0	66	0	2	26700	3	0	7	20	25	80010	10	80000	10	80000	50	1166277	0	1	0	49	23634	26737	26715	16682	3	16717	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80020	19	43	80019	1	0	1	21	80039	0	0	59	43	19	2	0	5021	0	1	16	16	15	17	26733	105	13	5	80000	10	26716	26738	26738	26737	26737
80024	26715	200	1	1	1	2	0	0	0	66	0	2	26721	0	7	7	19	25	80010	10	80000	10	80000	50	1168286	0	1	0	49	23657	26736	26737	16660	3	16716	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80020	21	0	80059	0	0	1	21	80040	6	1	59	0	19	2	0	5021	0	1	17	16	17	17	26733	103	13	0	80000	10	26716	26738	26738	26737	26716
80024	26736	200	1	1	0	2	1	0	0	21	0	2	26700	2	7	0	19	25	80010	10	80000	10	80000	50	1167791	0	1	0	49	23656	26736	26715	16681	3	16694	80010	20	80000	20	160000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	1	10	80019	21	43	80059	1	0	2	61	80040	6	0	58	43	19	2	0	5021	0	1	9	16	17	9	26733	103	0	5	80000	10	26716	26738	26738	26738	26715
80024	26736	200	1	1	0	1	1	0	0	70	0	2	26722	0	7	9	19	25	80010	10	80000	10	80000	50	1173975	0	1	0	49	23656	26737	26736	16681	3	16716	80010	20	80000	20	160000	26737	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	21	43	80059	1	0	1	61	80040	6	1	58	0	19	1	0	5021	0	1	17	16	17	14	26733	104	0	0	80000	10	26747	26738	26750	26716	26715

LDRSH (register, lsl, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations