Firestorm: LDRSH (32-bit) measurements

Code:

  ldrsh w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	1	1	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15267	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1039	38	1038	6	1	39	43	73	1	16	1	1	395	14	10	7	1000	399	399	399	399	399
1004	398	3	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15037	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1039	38	1038	6	1	39	43	73	1	16	1	1	391	14	14	7	1000	395	399	395	395	399
1004	394	2	0	1	0	44	0	0	1	386	2	12	12	16	25	1000	1000	1000	15274	0	394	398	221	3	252	1000	1000	1000	397	77	1	1	1001	1000	1000	1000	43	1038	39	1038	6	1	39	44	73	1	16	1	1	395	14	10	4	1000	399	399	399	399	395
1004	394	3	0	0	0	45	1	0	1	383	2	12	12	19	25	1000	1000	1000	15274	0	394	394	216	3	252	1000	1000	1000	394	77	1	1	1001	1000	1000	1000	43	1039	39	1039	6	1	36	44	73	1	16	1	1	391	10	10	4	1000	399	399	399	399	395
1004	398	2	0	1	0	44	1	0	1	382	2	1	1	16	25	1000	1000	1000	15274	0	398	394	221	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	1000	43	1038	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	395	399	399
1004	398	3	0	1	0	44	0	0	1	383	2	12	12	16	25	1000	1000	1000	14989	0	398	398	217	3	256	1000	1000	1000	394	77	1	1	1001	1000	1000	1000	43	1038	38	1039	6	1	39	43	73	1	16	1	1	391	14	14	7	1000	400	399	399	395	399
1004	394	3	0	1	0	45	1	0	1	383	2	1	1	19	25	1000	1000	1000	15208	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1038	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	2	0	1	0	45	0	0	1	379	2	12	1	19	25	1000	1000	1000	14989	1	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1038	38	1038	6	1	39	44	73	1	16	1	1	391	14	10	4	1000	399	395	395	395	399
1004	394	3	0	1	0	44	0	0	1	383	2	12	12	16	25	1000	1000	1000	14989	1	398	394	216	3	252	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1038	38	1038	6	1	39	43	73	1	16	1	1	391	14	14	7	1000	399	399	399	395	399
1004	398	3	0	1	0	45	1	0	1	383	2	12	12	16	25	1000	1000	1000	15037	0	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1000	43	1038	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	395	395	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	1	0	1	1	1	0	2	0	1	0	0	70041	69787	59712	25	40108	30106	10002	30100	10000	616032	3342494	0	49	66973	70056	70053	64637	3	64988	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	1	1	10000	1	1	1	1	0	2610	2	71	1	1	69819	30006	9	6	9	10000	30100	70060	70054	70054	70060	70057
40204	70056	526	1	0	1	0	1	0	1	0	1	0	0	70041	69784	59701	38	40104	30106	10002	30100	10000	616078	3342494	0	49	66976	70041	70056	64652	3	64959	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	3	1	10001	0	2	1	10000	1	1	1	1	0	2610	1	71	1	1	69819	30006	6	6	9	10000	30100	70057	70054	70057	70057	70057
40204	70056	525	1	1	0	0	0	0	2	0	1	0	0	70038	69787	59712	25	40104	30106	10002	30100	10000	616059	3342494	0	49	66976	70056	70053	64652	3	64959	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	1	1	4	10000	1	1	0	1	1	2610	1	71	1	1	69819	30003	9	9	9	10000	30100	70042	70042	70057	70057	70057
40204	70056	525	1	1	0	0	0	0	685	0	0	0	0	70041	69715	59716	25	40108	30106	10002	30100	10000	616078	3342494	0	49	66961	70041	70056	64652	3	64959	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	3	0	10002	0	1	1	10000	1	1	1	1	0	2610	1	71	1	1	69816	30003	0	6	9	10000	30100	70057	70057	70042	70057	70057
40204	70041	524	1	1	1	0	0	0	2	0	1	0	0	70041	69787	59701	25	40108	30106	10002	30100	10000	616059	3342494	0	49	66976	70053	70041	64637	3	64944	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10002	0	2	1	10000	1	1	0	1	0	2610	1	71	1	1	69819	30006	9	0	9	10000	30100	70042	70054	70042	70054	70042
40204	70041	524	1	1	0	0	0	0	1	0	0	0	1	70026	69702	59715	25	40108	30103	10002	30100	10000	616059	3342494	0	49	66976	70041	70053	64652	3	64956	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	0	1	10000	0	1	1	1	1	2610	1	71	1	1	69804	30006	9	9	0	10000	30100	70057	70057	70042	70045	70042
40204	70056	525	1	0	1	0	1	0	2	0	1	0	0	70038	69784	59701	25	40104	30106	10002	30100	10000	616078	3342494	0	49	66961	70053	70041	64652	3	64959	40100	30200	10000	60200	10000	70084	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	0	10001	1	1	1	10000	0	1	0	1	0	2610	1	71	1	1	69819	30006	9	6	0	10000	30100	70042	70042	70054	70057	70057
40204	70056	525	1	1	1	0	0	0	2	0	1	0	0	70041	69702	59712	25	40108	30103	10002	30100	10000	616059	3341769	0	49	66976	70041	70056	64652	3	64944	40100	30200	10000	60200	10000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10001	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69819	30006	9	9	9	10000	30100	70054	70042	70057	70057	70057
40204	70053	525	1	1	0	0	0	0	2	0	0	0	0	70038	69787	59701	25	40104	30106	10002	30100	10000	616059	3342494	0	49	66961	70056	70041	64637	3	64959	40100	30200	10000	60200	10064	70061	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	1	1	1	10000	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	0	9	10000	30100	70057	70057	70057	70057	70057
40204	70056	524	1	0	0	0	0	0	1	0	0	0	1	70026	69787	59715	25	40104	30106	10002	30100	10000	616059	3341769	0	49	66976	70056	70056	64637	3	64959	40100	30200	10000	60200	10000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	1	10001	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69819	30006	9	0	9	10000	30100	70057	70054	70042	70057	70057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70063	527	0	0	0	0	1	0	0	0	13	0	1	0	70032	69954	59695	25	40014	30013	10001	30010	10000	616982	3342206	0	0	49	66967	70047	70047	64668	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	0	10000	1	1	0	2520	0	1	71	1	2	69810	30003	0	6	9	10000	30010	70048	70051	70036	70036	70051
40024	70035	524	0	0	0	0	0	0	0	0	1	0	1	0	70032	69760	59695	25	40014	30013	10001	30010	10000	616952	3342206	0	0	49	66967	70050	70035	64665	3	64975	40010	30020	10000	61344	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	3	10000	1	0	0	2520	0	3	71	3	1	69798	30003	6	0	6	10000	30010	70048	70048	70048	70036	70049
40024	70047	525	0	0	0	0	0	0	0	0	1	0	1	0	70035	69743	59709	25	40014	30013	10001	30010	10000	616982	3342062	0	0	49	66967	70055	70418	64668	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	0	10000	1	0	0	2520	0	1	71	1	2	69810	30003	0	6	6	10000	30010	70053	70048	70048	70048	70048
40024	70035	524	0	0	0	0	0	0	0	0	1	0	0	0	70032	69760	59709	25	40010	30013	10000	30010	10000	617068	3342062	0	0	49	66970	70050	70050	64668	3	64972	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	9	10012	1	0	0	2520	0	2	71	2	1	69810	30000	6	6	6	10000	30010	70048	70036	70048	70048	70048
40024	70050	524	0	1	0	0	0	0	0	0	1	0	0	0	70032	69728	59706	25	40010	30013	10012	30010	10000	616952	3341470	0	0	49	66967	70047	70049	64670	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	2	0	12	10000	1	1	0	2520	0	1	71	2	1	69813	30003	0	9	9	10000	30010	70048	70036	70048	70036	70054
40024	70050	525	0	0	0	0	0	0	0	0	0	0	0	0	70020	69728	59695	25	40064	30010	10001	30010	10000	616952	3342062	1	0	49	66971	70037	70416	64668	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	0	10000	1	1	0	2520	0	2	71	2	1	69810	30003	0	6	6	10000	30010	70036	70048	70036	70048	70036
40024	70035	525	0	0	0	0	1	0	0	0	1	0	0	0	70020	69760	59710	25	40014	30049	10000	30010	10000	616982	3342206	0	0	49	66970	70047	70050	64653	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	0	0	10000	1	1	0	2520	0	1	71	1	2	69810	30000	6	6	6	10000	30010	70048	70048	70048	70036	70048
40024	70047	524	0	0	0	0	0	0	0	0	0	0	0	0	70032	69743	59695	25	40014	30013	10000	30584	10000	617068	3342062	0	0	49	66968	70052	70035	64653	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	1	0	8879	10000	1	0	0	2520	0	1	71	2	3	69810	30003	0	6	6	10000	30010	70048	70048	70048	70048	70051
40024	70047	525	0	0	0	0	0	0	0	0	13	0	1	0	70032	69736	59706	25	40014	30013	10001	30010	10000	617068	3342062	0	0	49	66967	70047	70035	64665	3	64972	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	0	10000	1	1	0	2520	0	2	79	1	2	69813	30000	9	9	6	10000	30010	70051	70051	70051	70051	70036
40024	70050	524	0	0	0	0	1	0	0	0	6	0	1	0	70032	69728	59706	25	40014	30010	10001	30010	10000	616952	3342062	0	0	49	66967	70047	70050	64665	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	0	10000	1	1	0	2520	0	1	71	1	2	69798	30003	9	9	9	10000	30010	70048	70048	70036	70051	70036

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]
  ldrsh w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	0	0	0	45	0	0	1	26712	2	0	12	16	25	80100	100	80000	100	80000	500	1177038	1	0	49	23657	26736	26736	16659	3	16695	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	80059	0	0	1	61	80040	6	1	39	43	0	0	0	5110	0	0	1	16	1	1	26724	0	10	10	0	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	21	1	0	2	26699	0	7	7	0	25	80100	100	80000	100	80000	500	1170073	1	0	49	23647	26727	26727	16630	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	0	80039	0	0	0	39	80039	6	1	39	43	0	0	0	5110	0	0	1	16	1	1	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	21	0	0	2	26721	2	7	7	19	25	80100	100	80000	100	80000	500	1167231	0	0	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	39	80039	6	1	59	43	18	1	0	5110	0	0	1	16	1	1	26724	0	10	0	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	45	1	0	1	26712	2	0	12	16	25	80100	100	80000	100	80000	500	1165789	0	0	49	23647	26707	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	80000	0	0	0	39	80039	6	1	39	0	0	0	0	5110	0	0	1	16	1	1	26724	0	10	10	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	45	1	0	1	26712	2	0	12	16	25	80100	100	80000	100	80000	500	1177038	1	0	49	23647	26727	26707	16650	3	16685	80100	200	80190	200	80000	26727	56	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	0	80039	6	1	39	43	0	0	1	5132	0	0	1	16	1	1	26704	0	10	10	4	80000	100	26728	26728	26708	26728	26728
80204	26727	200	0	1	0	0	0	21	0	0	3	26699	0	7	7	20	25	80100	100	80000	100	80000	500	1166519	1	0	49	23647	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	80039	0	0	0	0	80000	6	1	39	43	0	0	0	5110	0	0	1	16	1	1	26724	0	10	10	4	80000	100	26728	26728	26728	26708	26728
80204	26727	200	0	0	1	0	0	72	1	0	1	26692	2	12	12	17	25	80100	100	80000	100	80000	500	1166525	1	0	49	23627	26727	26707	16630	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	39	80039	6	1	0	43	0	0	0	5110	5	2	1	16	1	1	26724	0	0	10	4	80000	100	26708	26708	26728	26708	26708
80204	26707	200	0	0	0	0	0	45	0	0	1	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1165789	1	0	49	23634	26714	26714	16659	3	16694	80100	200	80000	200	80000	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	43	80058	1	0	1	60	80040	0	1	39	0	0	0	0	5110	0	0	1	16	1	1	26724	0	10	10	0	80000	100	26708	26728	26728	26728	26708
80204	26727	200	0	1	1	0	0	67	1	0	2	26721	3	0	0	0	25	80100	100	80000	100	80000	500	1167231	0	5	49	23647	26727	26819	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	0	80000	0	0	0	40	80039	6	1	58	0	19	1	0	5110	5	3	1	16	1	1	26704	0	10	10	4	80000	100	26728	26708	26728	26708	26728
80204	26727	200	0	0	0	1	0	45	0	0	1	26712	3	0	12	16	25	80100	100	80000	100	80000	500	1166525	1	5	49	23635	26727	26727	16650	3	16685	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	0	100	80000	100	80000	1	100	80000	0	43	80000	0	0	0	39	80039	6	0	39	43	0	0	0	5110	5	3	1	16	1	1	26724	0	10	10	4	80000	100	26728	26708	26735	26728	26728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	201	1	0	0	0	0	0	2	26712	2	12	0	0	25	80010	10	80000	10	80000	50	1166818	0	1	49	23647	26722	26728	16672	3	16702	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	80035	0	188	80035	6	0	0	39	5020	20	16	9	6	26719	10	0	2	80000	10	26709	26723	26723	26723	26728
80024	26866	200	0	0	0	0	0	0	1	26712	0	18	18	12	25	80010	10	80000	10	80000	50	1169410	0	0	49	23642	26708	26708	16667	3	16702	80010	20	80220	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	35	80039	6	1	35	0	5020	9	16	9	6	26724	10	0	4	80000	10	26729	26729	26729	26729	26723
80024	26722	202	0	0	0	41	1	0	1	26707	2	0	12	12	25	80010	10	80000	10	80000	50	1168276	0	1	49	23642	26708	26722	16667	12	16702	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80165	1	35	80000	0	1	0	39	5020	6	16	11	10	26719	6	0	2	80000	10	26723	26728	26709	26729	26709
80024	26722	200	0	0	0	45	1	0	2	26712	0	12	12	0	25	80010	10	80000	10	80000	50	1166801	0	1	49	23648	26722	26708	16672	3	16702	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80036	0	35	80039	0	1	35	43	5020	5	16	9	6	26705	10	0	4	80000	10	26709	26728	26728	26728	26728
80024	26722	201	1	0	0	0	0	0	1	26693	2	0	18	12	25	80010	10	80000	10	80000	50	1166996	0	1	49	23642	26722	26722	16667	3	16702	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	35	80035	6	1	0	0	5020	10	16	9	8	26719	0	0	2	80000	10	26709	26723	26723	26723	26723
80024	26722	200	0	0	0	0	0	0	1	26693	2	18	18	16	25	80010	10	80000	10	80000	50	1179515	0	1	49	23642	26708	26708	16652	3	16702	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	35	80035	6	1	35	39	5020	6	16	7	5	26705	10	6	0	80000	10	26729	26729	26723	26729	26723
80024	26722	201	0	0	0	0	1	0	2	26713	2	12	12	0	25	80010	10	80000	10	80000	50	1171885	0	1	49	23628	26708	26722	16672	3	16688	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	35	80000	6	1	0	39	5020	9	16	8	7	26719	6	6	2	80000	10	26723	26709	26723	26723	26723
80024	26722	202	0	0	0	41	1	0	1	26707	2	18	0	0	25	80010	10	80000	10	80000	50	1169101	0	1	49	23628	26722	26708	16667	3	16702	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	191	80035	6	1	35	39	5020	9	16	8	8	26719	6	0	2	80000	10	26723	26723	26723	26723	26723
80024	26708	201	0	0	1	41	0	0	1	26712	2	12	18	16	25	80010	10	80000	10	80000	50	1172240	0	1	49	23647	26728	26727	16652	3	16708	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	38	80000	6	1	35	0	5020	7	16	9	5	26705	0	6	4	80000	10	26729	26709	26729	26723	26709
80025	26899	200	0	1	0	0	1	0	2	26693	2	0	12	16	25	80010	10	80000	10	80000	50	1167209	0	1	49	23642	26708	26708	16652	3	16688	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	35	80035	6	1	35	43	5020	8	16	10	9	26705	6	6	0	80000	10	26723	26709	26723	26723	26760

LDRSH (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations