Firestorm: LDRB (register, uxtw) measurements

Code:

  ldrb w0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15267	0	394	394	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	6	1	39	44	73	1	16	1	1	395	10	10	4	1000	404	402	399	399	399
1004	398	3	0	0	0	44	0	0	1	383	2	1	12	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	43	73	1	16	1	1	391	10	10	7	1000	399	395	395	399	395
1004	394	3	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15018	1	394	398	221	3	252	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	39	1038	6	1	38	44	73	1	16	1	1	391	10	10	7	1000	399	399	399	399	399
1004	398	3	0	0	0	45	1	0	1	383	2	12	1	19	25	1000	1000	1000	15274	0	394	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15037	0	398	394	279	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	395	399	400
1004	398	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15018	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1039	6	1	39	44	73	1	16	1	1	395	10	14	7	1000	395	399	399	399	399
1004	398	3	0	1	1	45	0	0	1	379	2	1	1	19	25	1000	1000	1000	15274	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	10	10	4	1000	399	395	395	395	399
1004	394	3	0	0	0	45	1	0	1	383	2	12	12	19	25	1000	1000	1000	15338	1	398	398	217	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	10	10	4	1000	399	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15274	0	398	394	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	44	0	0	1	379	2	12	1	16	25	1000	1000	1000	15274	1	398	398	221	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	1	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	10	14	7	1000	399	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	2	1	0	0	0	1	1	0	70036	69796	59740	25	40104	30103	10001	30100	10000	616175	3342254	1	49	66974	70054	70051	64650	0	3	64957	40100	30200	10000	60200	20000	70052	35	1	1	40202	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	2610	3	71	1	1	69817	30000	13	0	13	10000	30100	70088	70088	70098	70055	70052
40204	70054	525	0	0	0	0	0	0	1	0	70036	69785	59800	25	40104	30103	10000	30100	10000	616041	3341470	1	49	66955	70054	70054	64631	0	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69817	30003	0	10	0	10000	30100	70062	70056	70052	70055	70036
40204	70035	525	0	1	0	0	0	1	1	0	70039	69784	59710	25	40100	30103	10001	30100	10000	616014	3342398	1	49	66971	70054	70054	64650	0	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	2	0	10000	1	0	0	10000	0	0	0	0	2610	1	71	1	1	69798	30003	0	0	0	10000	30100	70056	70053	70055	70055	70036
40204	70054	524	0	0	1	0	0	1	0	0	70036	69785	59713	25	40100	30103	10001	30100	10000	616041	3341470	1	49	63946	70058	70054	64631	0	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69798	30000	13	10	13	10000	30100	70055	70038	70036	70036	70055
40204	70054	525	0	0	0	0	0	1	1	0	70020	69788	59695	25	40104	30103	10001	30100	10000	616041	3342398	1	49	66974	70054	70035	64650	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	10	13	13	10000	30100	70110	70057	70052	70055	70055
40204	70035	525	0	0	0	0	0	1	0	0	70020	69785	59713	25	40100	30103	10001	30100	10000	616014	3342398	1	49	66974	70054	70035	64650	0	3	64954	40100	30398	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	1	0	2610	1	71	1	1	69798	30000	10	10	13	10000	30100	70091	70052	70054	70052	70055
40204	70051	525	0	0	0	0	0	0	1	0	70020	69793	59713	25	40100	30100	10001	30100	10000	616175	3342398	1	49	66955	70035	70035	64650	0	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10000	1	1	0	0	2610	1	71	1	1	69817	30003	10	10	0	10000	30100	70089	70057	70036	70055	70055
40204	70054	525	0	0	0	0	0	6	0	0	70039	69786	59710	25	40100	30103	10000	30100	10000	616041	3341470	1	49	66955	70035	70054	64650	0	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	4	0	10000	0	0	0	10000	0	0	0	0	2610	1	71	1	1	69798	30000	10	13	0	10000	30100	70057	70059	70052	70036	70055
40204	70054	525	0	0	0	0	0	0	1	0	70036	69786	59695	25	40104	30103	10001	30100	10000	616014	3342398	0	49	66974	70035	70054	64650	0	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	1	0	0	10000	1	1	0	1	2610	1	71	1	1	69817	30000	13	13	0	10000	30100	70092	70039	70053	70052	70055
40205	70035	524	0	0	0	0	0	1	1	0	70039	69785	59714	25	40100	30103	10001	30100	10000	616014	3342398	1	49	66974	70035	70054	64650	0	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69817	30000	0	0	13	10000	30100	70075	70088	70052	70052	70096

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	1	0	1	1	0	1	0	0	0	0	7	0	0	0	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3341769	1	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10002	0	0	0	1	10000	1	1	1	1	2	2520	15	71	0	13	5	69820	30006	10	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	524	1	0	0	1	0	1	0	0	0	0	2	0	1	0	0	2	70042	69781	59716	25	40018	30016	10002	30010	10000	616995	3342542	1	49	66977	70057	70057	64675	3	64966	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	0	0	1	10000	1	1	1	1	0	2520	14	71	0	14	14	69820	30006	10	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	525	1	0	0	1	0	1	0	0	0	0	7	0	0	0	0	1	70042	69781	59748	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	1	0	1	10000	1	1	1	1	0	2520	14	71	0	14	14	69820	30006	10	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	525	1	0	1	1	0	0	1	1	0	0	2	0	1	0	0	1	70080	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10037	1	1	10043	0	1	3	36194	10048	1	1	1	1	0	2912	20	200	0	8	16	71080	30166	10	10	10	10000	30010	71604	71626	70965	71612	71505
40024	71597	531	1	0	2	2	2	2	0	0	11	17	2138	1496	1	0	0	1	71576	70265	60445	469	40216	30180	10053	32459	10510	654255	3385980	1	49	68476	71004	71606	65290	148	66006	42411	32952	10669	65920	21982	71151	35	19	1	40021	10	9	10	10000	30010	10000	0	10	10058	4	1	10040	0	1	3	38526	10057	1	1	1	1	3	3020	25	233	0	19	11	71316	30189	10	10	10	10000	30010	71966	71774	71892	71938	71962
40024	72046	539	1	4	0	2	0	2	0	0	12	15	1327	1144	1	0	0	2	71320	70331	60150	396	40169	30121	10035	31594	10816	647887	3370955	1	49	68174	70319	70057	64675	3	64966	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10001	0	0	0	1	10000	1	1	1	1	1	2520	14	71	0	14	14	69820	30006	10	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	525	1	0	1	1	0	1	0	0	0	0	2	0	1	0	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	63944	70057	70057	64675	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	0	1	10000	1	1	1	1	0	2520	14	71	0	14	5	69820	30006	10	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	525	1	0	1	0	0	1	0	0	0	0	2	0	1	0	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	1	0	1	10000	1	1	1	1	0	2520	14	71	0	14	14	69820	30006	10	10	10	10000	30010	70058	70058	70058	70042	70058
40024	70057	525	1	0	1	1	0	1	0	0	0	0	7	0	1	0	0	1	70042	69702	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	70057	70057	64675	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	1	1	10000	1	1	1	1	1	2520	14	71	0	14	5	69820	30006	10	10	10	10000	30010	70058	70058	70058	70058	70058
40024	70057	525	1	0	1	1	0	1	0	0	0	0	2	0	1	0	0	1	70042	69781	59716	25	40018	30016	10002	30010	10000	617045	3342542	1	49	66977	70057	70057	64675	3	64984	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	2	1	10000	1	1	1	1	2	2520	14	71	0	14	4	69820	30006	0	10	10	10000	30010	70058	70058	70061	70058	70058

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	0	0	1	0	0	0	70032	69781	59695	25	40104	30103	10001	30100	10000	616015	3342206	49	66970	70041	70050	64646	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	9	6	9	10000	30100	70048	70048	70048	70048	70048
40204	70050	524	0	0	0	1	0	1	0	70032	69781	59706	25	40104	30103	10000	30100	10000	616005	3342062	49	66970	70047	70050	64646	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	0	2610	1	71	1	1	69810	30000	9	0	9	10000	30100	70051	70051	70036	70051	70051
40204	70035	524	0	0	0	1	0	0	0	70082	69735	59709	25	40104	30103	10001	30100	10000	616005	3342206	49	66970	70050	70035	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69855	30003	6	6	9	10000	30100	70051	70048	70048	70048	70048
40204	70050	525	0	0	0	1	0	0	0	70032	69735	59706	25	40104	30103	10000	30100	10000	616005	3342206	49	66970	70047	70050	64646	3	64953	40100	30200	10000	61492	20000	70063	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	9	6	6	10000	30100	70051	70051	70048	70048	70051
40204	70047	524	0	0	0	1	0	1	0	70032	69735	59709	25	40104	30100	10001	30100	10000	616005	3342206	49	66970	70035	70047	64646	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30000	9	0	6	10000	30100	70048	70036	70036	70036	70048
40204	70050	525	0	0	0	1	0	1	0	70035	69735	59706	25	40104	30100	10000	30100	10000	616005	3342206	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30003	9	6	6	10000	30100	70048	70051	70051	70051	70051
40204	70035	524	0	0	0	0	0	1	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616005	3342206	49	66970	70035	70047	64646	3	64950	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69810	30000	0	6	9	10000	30100	70048	70048	70048	70036	70048
40204	70047	524	0	0	0	0	0	1	0	70020	69781	59709	25	40104	30103	10001	30100	10000	616175	3342206	49	66970	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69813	30003	9	0	9	10000	30100	70051	70036	70051	70051	70051
40204	70047	525	0	1	0	1	0	0	0	70032	69735	59695	25	40104	30103	10001	30100	10000	616005	3341470	49	66967	70050	70047	64646	3	64950	40100	30200	10000	61522	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	3	10003	1	1	0	0	2610	1	71	1	1	69810	30003	9	6	9	10000	30100	70051	70048	70048	70048	70048
40204	70050	524	0	1	0	1	0	0	0	70020	69781	59706	25	40104	30103	10001	30100	10000	616005	3342206	49	66970	70050	70035	64643	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	2610	1	71	1	1	69813	30000	0	9	9	10000	30100	70048	70051	70051	70051	70048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	1	1	1	1	0	0	2	1	0	70041	69770	59710	25	40014	30013	10001	30010	10000	616982	3342062	1	0	49	66955	0	70050	70050	64668	0	3	64975	40205	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	0	0	2	71	2	1	69813	30003	9	6	28	10000	30010	70051	70051	70048	70051	70051
40024	70056	525	1	1	1	1	0	0	2	0	0	70041	69780	59715	25	40018	30016	10002	30010	10000	617036	3342494	1	5	49	66976	0	70056	70056	64720	0	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	5	1	1	71	1	1	69813	30003	9	6	27	10000	30010	70051	70051	70051	70036	70036
40024	70050	525	0	0	0	0	0	0	1	0	0	70035	69760	59709	25	40014	30013	10001	30010	10000	616982	3342206	1	5	49	66970	0	70050	70050	64665	0	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	5	1	1	71	1	2	69813	30003	9	6	27	10000	30010	70110	70053	70048	70048	70036
40024	70050	525	0	0	0	0	1	0	0	0	0	70032	69728	59709	25	40014	30013	10001	30010	10000	616952	3341470	1	5	49	66967	0	70050	70047	64653	0	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	0	0	2520	5	2	1	71	1	2	69810	30003	9	6	27	10000	30010	70051	70051	70051	70048	70051
40024	70050	524	0	0	0	0	0	0	1	1	0	70020	69760	59702	25	40014	30013	10001	30010	10000	616991	3342254	1	5	49	66970	0	70050	70035	64668	0	3	64961	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	2520	5	2	2	71	1	2	69798	30003	9	6	20	10000	30010	70051	70051	70051	70051	70036
40024	70035	524	0	0	0	0	0	0	1	0	0	70035	69760	59709	25	40010	30013	10001	30010	10000	616952	3342062	1	5	49	66970	3	70050	70035	64665	0	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	5	2	2	71	1	1	69813	30000	9	9	27	10000	30010	70051	70051	70048	70051	70051
40024	70050	525	0	0	0	0	0	0	1	0	0	70035	69760	59709	25	40014	30013	10001	30010	10000	616982	3341470	1	5	49	66967	0	70047	70047	64668	0	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	5	2	2	71	1	2	69813	30003	9	6	27	10000	30010	70051	70051	70051	70036	70048
40024	70050	525	0	0	0	0	0	0	1	0	0	70035	69760	59709	25	40014	30022	10001	30010	10000	616982	3342062	1	5	49	66970	3	70047	70047	64668	0	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	5	2	1	71	1	2	69813	30003	9	6	27	10000	30010	70051	70036	70036	70048	70036
40024	70050	525	0	0	0	0	0	0	1	1	0	70035	69760	59709	25	40014	30013	10001	30010	10000	616982	3342206	1	5	49	66967	0	70050	70050	64668	0	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10003	0	0	0	10000	1	0	1	0	0	0	0	2520	5	2	1	71	1	1	69813	30003	9	6	27	10000	30010	70051	70051	70048	70048	70051
40024	70050	525	0	0	0	0	0	1	1	0	0	70035	69760	59709	25	40010	30013	10001	30010	10000	616982	3342206	1	5	49	66967	0	70047	70050	64665	0	3	64975	40010	30020	10000	60020	20000	70177	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	2520	5	2	1	71	1	1	69816	30000	9	9	27	10000	30010	70051	70036	70051	70051	70051

Test 4: throughput

Count: 8

Code:

  ldrb w0, [x6, w7, uxtw]
  ldrb w0, [x6, w7, uxtw]
  ldrb w0, [x6, w7, uxtw]
  ldrb w0, [x6, w7, uxtw]
  ldrb w0, [x6, w7, uxtw]
  ldrb w0, [x6, w7, uxtw]
  ldrb w0, [x6, w7, uxtw]
  ldrb w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	1	1	45	1	0	2	26692	2	18	18	12	25	80100	100	80000	100	80015	500	1177116	1	49	23627	26707	26727	16655	6	16753	80115	200	80024	200	160048	26727	72	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	0	80035	0	35	80039	6	1	0	0	1	1	1	5118	0	16	0	0	26724	0	6	4	80000	100	26723	26708	26723	26723	26723
80204	26722	200	0	0	45	1	0	2	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	1	49	23627	26727	26707	16655	6	16679	80114	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80000	0	35	80039	6	1	35	43	1	1	1	5118	0	16	0	0	26704	0	10	4	80000	100	26723	26723	26723	26708	26723
80204	26727	200	0	0	0	0	0	0	26712	2	18	18	0	25	80100	100	80000	100	80015	500	1166596	1	49	23627	26722	26722	16655	6	16674	80115	200	80024	200	160048	26707	72	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80000	0	0	80000	6	1	35	43	1	1	1	5118	0	16	0	0	26724	10	6	4	80000	100	26708	26708	26723	26708	26728
80204	26722	200	0	0	0	1	0	2	26712	0	12	12	0	25	80100	100	80000	100	80015	500	1177116	1	49	23647	26727	26727	16655	6	16674	80114	200	80024	200	160048	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80035	0	0	80000	6	0	0	43	1	1	1	5118	0	16	0	0	26719	10	0	4	80000	100	26728	26708	26723	26708	26708
80204	26727	200	0	0	41	0	0	0	26692	2	12	0	16	25	80100	100	80000	100	80014	500	1167303	1	49	23627	26727	26727	16635	6	16674	80115	202	80216	200	160048	26711	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	0	80039	0	0	35	43	1	1	1	5118	0	16	0	0	26719	0	6	0	80000	100	26743	26723	26708	26730	26726
80204	26727	200	0	0	45	0	0	2	26692	0	0	0	16	25	80100	100	80000	100	80014	500	1167303	1	49	23647	26727	26727	16655	6	16864	80116	200	80024	200	160048	26728	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	3	80039	6	1	0	0	1	1	1	5118	0	16	0	0	26724	10	0	4	80000	100	26708	26708	26708	26723	26728
80204	26707	200	0	0	45	0	0	2	26712	0	18	12	0	25	80100	100	80000	100	80015	500	1167303	1	49	23647	26722	26727	16635	6	16674	80115	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80035	0	39	80039	6	0	35	0	1	1	1	5118	0	16	0	0	26704	10	6	4	80000	100	26723	26728	26728	26728	26708
80204	26727	200	0	0	41	1	0	0	26692	0	12	18	16	25	80100	100	80000	100	80015	500	1166596	1	49	23642	26727	26722	16650	6	16674	80114	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80000	0	39	80000	0	0	35	43	1	1	1	5118	0	16	0	0	26724	0	10	2	80000	100	26708	26723	26728	26708	26728
80204	26727	200	0	0	0	0	0	0	26712	2	12	0	16	25	80100	100	80000	100	80016	500	1166596	1	49	23647	26727	26727	16655	6	16679	80116	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	39	80039	6	0	35	0	1	1	1	5118	0	16	0	0	26704	10	0	4	80000	100	26728	26728	26708	26728	26708
80204	26727	200	0	0	41	1	0	0	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	1	49	23647	26722	26727	16655	6	16674	80115	202	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80035	0	39	80039	0	1	0	0	1	1	1	5118	0	16	0	0	26704	6	6	4	80000	100	26723	26708	26728	26723	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	l2 tlb miss data (0b)	0e	0f	18	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	0	0	0	0	0	45	1	1	26721	2	12	12	19	25	80010	10	80000	10	80000	50	1168843	1	0	49	23647	26708	26728	16672	3	16688	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	42	80039	6	0	39	44	5020	0	4	16	4	7	26724	10	10	4	80000	10	26728	26709	26729	26728	26728
80024	26708	200	0	0	0	0	0	45	1	1	26717	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	0	49	23628	26727	26708	16672	3	16688	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80000	1	39	80039	6	0	39	43	5020	0	6	16	6	6	26724	0	10	4	80000	10	26729	26729	26728	26729	26728
80024	26727	200	0	0	0	0	0	45	1	1	26719	3	0	12	16	25	80010	10	80000	10	80000	50	1168843	0	0	49	23628	26727	26727	16672	3	16707	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80039	0	39	80039	6	1	39	43	5020	0	7	16	4	3	26724	10	10	4	80000	10	26709	26729	26728	26729	26728
80024	26728	200	0	0	0	0	0	6	1	1	26722	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	0	49	23628	26708	26708	16672	3	16707	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	39	80039	0	1	39	0	5020	0	4	16	4	3	26725	0	10	0	80000	10	26729	26728	26728	26728	26729
80024	26728	200	0	0	0	0	0	45	1	1	26718	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	0	0	49	23647	26727	26728	16672	3	16707	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	39	80000	6	1	39	43	5020	0	4	16	5	8	26725	10	10	4	80000	10	26728	26729	26729	26728	26728
80024	26728	200	0	0	0	1	0	45	1	1	26700	0	0	0	16	25	80010	10	80000	10	80000	50	1166750	0	0	49	23628	26728	26728	16652	3	16688	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	39	80039	6	1	39	43	5020	0	4	16	6	6	26724	10	10	4	80000	10	26729	26729	26728	26728	26729
80024	26728	201	0	0	0	0	0	45	1	0	26723	2	12	12	16	25	80010	10	80000	10	80000	50	1168843	0	0	49	23648	26728	26727	16672	3	16707	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	43	80000	0	39	80039	6	0	39	43	5020	0	7	16	7	6	26724	10	10	4	80000	10	26728	26729	26729	26728	26728
80024	26728	200	0	0	0	0	0	45	1	1	26721	3	12	12	19	25	80010	10	80000	10	80000	50	1166896	0	0	49	23647	26728	26728	16672	3	16708	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	39	80039	6	1	39	43	5020	0	3	16	6	4	26725	0	10	4	80000	10	26729	26728	26729	26709	26728
80024	26708	200	0	0	0	0	0	45	1	1	26698	2	12	12	0	25	80010	10	80000	10	80000	50	1168843	0	0	49	23648	26727	26728	16652	3	16707	80010	20	80000	20	160000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80039	0	39	80039	6	1	39	43	5020	0	4	16	4	3	26724	0	10	4	80000	10	26728	26728	26709	26729	26728
80024	26728	200	0	0	1	0	0	45	0	1	26693	0	12	12	16	25	80010	10	80000	10	80000	50	1166896	0	0	49	23647	26728	26728	16672	3	16688	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80039	0	39	80039	6	1	39	43	5020	0	7	16	3	4	26725	10	10	0	80000	10	26713	26728	26729	26709	26709

LDRB (register, uxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations