Firestorm: LDRB (post-index) measurements

Code:

  ldrb w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0f	1e	20	22	24	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	8	0	0	60	0	0	0	4	0	1025	15	3	19	4	14	25	2000	1000	1000	1000	1000	52820	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1044	44	1	1	1001	1000	1000	0	1000	0	1	59	1042	5	0	16	12	18	1032	70	2	18	56	73	1	16	1	1	1037	1000	21	18	0	1000	1000	1041	1041	1041	1041	1041
2004	1041	8	0	0	64	22	1	0	2	0	1025	15	3	8	8	16	25	2000	1000	1000	1000	1000	52832	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1028	0	1	43	1031	2	0	17	8	18	1032	35	3	15	56	73	1	16	1	1	1037	1000	20	22	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	86	0	0	0	5	0	1033	9	5	11	13	23	25	2000	1000	1000	1000	1000	52800	45822	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1000	0	0	56	1018	0	1	0	0	23	1018	33	4	18	88	73	1	16	1	1	1037	1000	31	21	0	1000	1000	1041	1041	1055	1041	1041
2004	1040	8	0	0	52	18	1	0	3	0	1025	13	2	19	10	19	25	2000	1000	1000	1000	1000	52832	45823	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1014	0	0	69	1039	1	0	18	8	13	1020	30	2	19	88	73	1	16	1	1	1037	1000	31	22	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	0	0	59	18	1	0	3	0	1025	15	6	15	8	17	25	2000	1000	1000	1000	1000	52816	45824	1	1041	1040	699	3	773	2000	1000	1000	1000	1000	1051	44	1	1	1001	1000	1000	0	1000	0	0	51	1025	0	0	16	6	16	1041	52	3	27	64	73	1	16	1	1	1037	1000	29	21	0	1000	1000	1045	1045	1041	1041	1041
2004	1040	8	0	0	52	0	0	0	3	0	1034	0	6	25	6	21	25	2000	1000	1000	1000	1000	52812	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1024	0	0	65	1019	0	0	0	0	18	1025	34	3	19	48	73	1	16	1	1	1037	1000	32	29	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	51	16	1	0	3	0	1025	26	3	13	6	18	25	2000	1000	1000	1000	1000	52808	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	2	1014	0	1	52	1028	6	0	16	8	12	1034	33	4	24	56	73	1	16	1	1	1037	1000	29	27	0	1000	1000	1049	1050	1050	1052	1052
2004	1040	8	0	0	52	0	0	0	2	0	1033	9	5	21	13	18	25	2000	1000	1000	1000	1000	52820	45823	0	1040	1044	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1008	0	0	48	1040	5	0	20	6	16	1022	43	2	28	72	73	1	16	1	1	1036	1000	36	34	5	1000	1000	1041	1041	1043	1041	1041
2004	1040	7	0	0	42	18	1	0	3	0	1025	9	3	14	8	15	25	2000	1000	1000	1000	1000	52816	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1014	0	1	43	1036	2	0	22	12	16	1045	39	4	34	56	73	1	16	1	1	1037	1000	24	27	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	0	0	63	0	0	0	5	12	1025	0	5	8	13	19	25	2000	1000	1000	1000	1000	52816	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1022	0	1	64	1018	0	0	0	12	30	1033	46	4	22	56	73	1	16	1	1	1037	1000	29	23	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1892

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	29	3a	3e	3f	40	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72332	538	2	0	0	0	0	447	797	1	728	3	108	71829	807	71606	25	50735	40664	10150	40100	10000	615132	2722429	0	49	68845	0	71796	71946	65484	3	65636	50100	40200	10000	70200	10000	72015	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10983	6	174	495	10645	279	15	912	38	24	10914	152	1	139	1	0	3	0	0	2610	2	58	1	1	71662	40536	1055	1131	1057	10000	40100	71926	71903	71846	71771	71944
50204	72043	539	2	0	0	0	0	469	820	1	736	1	120	71902	817	71603	25	50770	40616	10120	40100	10000	614962	2721436	1	49	68899	0	71913	71963	65468	3	65472	50100	40200	10000	70200	10000	71883	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10905	1	171	478	10645	263	16	902	76	24	10932	130	1	125	1	0	4	0	0	2610	1	58	1	1	71684	40484	1050	1030	1028	10000	40100	71648	71884	71890	72027	71903
50204	71874	539	3	1	0	0	0	397	795	1	712	1	120	71983	808	71460	25	50755	40584	10128	40100	10000	614118	2729543	0	49	68744	0	71887	71891	65387	3	65554	50100	40200	10000	70200	10000	71980	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10887	1	163	460	10643	250	11	927	36	34	10901	137	1	126	1	0	4	0	0	2610	1	58	1	1	71617	40520	1120	900	1076	10000	40100	71790	71883	71756	71886	71838
50204	71976	538	2	0	0	0	0	516	836	1	680	2	132	71781	796	71613	25	50765	40640	10133	40100	10000	615840	2724968	1	49	68687	0	71954	71961	65276	3	65580	50100	40200	10000	70200	10000	71946	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10901	2	144	486	10626	260	14	945	76	29	10913	117	2	130	2	0	3	0	0	2610	1	58	1	1	71772	40528	1148	1084	1026	10000	40100	71888	71867	71963	71849	71766
50204	71944	540	3	0	0	0	0	454	817	1	696	2	116	71795	807	71462	25	50735	40616	10141	40100	10000	614669	2728574	1	49	68936	0	71912	71998	65323	3	65404	50100	40200	10000	70200	10000	71879	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10926	2	153	495	10636	282	9	908	84	32	10932	129	2	137	2	3	3	0	0	2610	1	58	1	1	71751	40500	1090	1083	999	10000	40100	71804	71767	71810	71883	71812
50204	71828	539	3	0	0	0	0	476	822	1	712	2	120	71805	806	71567	25	50725	40596	10132	40100	10000	616434	2727177	1	49	68848	0	72014	71790	65200	3	65634	50100	40200	10000	70200	10000	71852	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10889	3	173	472	10646	286	12	928	76	30	10897	134	3	133	3	0	5	0	1	2610	1	58	1	1	71791	40496	1138	1150	1052	10000	40100	71871	71953	71793	71820	72072
50204	71973	539	2	0	0	0	0	454	812	1	720	1	120	71946	822	71697	25	50720	40692	10140	40100	10000	616114	2726905	1	49	68818	0	71783	71859	65233	3	65431	50100	40200	10000	70200	10000	71800	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10932	1	157	492	10632	274	12	914	52	34	10931	135	1	129	1	1	11	1	0	2610	1	58	1	1	71771	40484	1071	971	1093	10000	40100	71788	72059	71804	71853	72017
50204	71873	538	3	0	0	2	0	497	808	1	728	2	112	71859	812	71608	25	50810	40644	10132	40100	10048	616822	2725308	1	49	68795	0	71964	71879	65368	3	65610	50100	40200	10000	70200	10000	71962	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10912	2	152	475	10668	276	9	888	48	22	10940	114	2	135	2	0	3	0	0	2610	0	87	1	1	71636	40520	1116	1033	1083	10000	40100	71960	71886	71983	71930	71952
50204	71796	539	2	0	0	1	1	448	813	1	744	1	140	71830	804	71574	25	50680	40572	10123	40100	10000	613856	2734530	0	49	68902	0	71839	71894	65305	3	65515	50100	40200	10000	70200	10000	71850	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10933	4	166	489	10661	276	11	892	76	25	10924	132	2	126	2	0	9	0	0	2610	1	58	1	1	71756	40500	1048	1069	1062	10000	40100	72063	71770	71849	71899	71972
50204	71892	538	3	0	0	0	0	465	801	1	720	2	104	72024	800	71745	25	50710	40620	10140	40100	10000	615264	2724689	1	49	68712	0	71890	71996	65421	3	65630	50100	40200	10000	70200	10000	71854	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10945	2	147	500	10644	259	14	904	76	20	10915	130	2	120	2	3	3	0	0	2610	1	58	1	1	71724	40488	1097	1074	1130	10000	40100	71878	71972	71899	71857	72108

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.2122

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72339	542	2	0	0	0	0	0	608	0	837	1	720	2	136	72117	805	42	14	71857	25	50895	40738	10186	40010	10000	613985	2732591	1	49	69068	72041	72073	65561	3	65788	50010	40020	10000	70020	10000	72109	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10957	1	143	503	10696	268	10	929	72	60	10946	122	36	132	1	4	4	0	0	2520	0	11	65	6	10	71846	40692	880	928	930	10000	40010	72088	72118	72093	72298	72296
50024	72106	539	2	0	0	0	0	0	556	0	819	1	728	3	100	72153	810	34	15	71963	25	50825	40726	10174	40010	10000	633232	2725932	0	49	69063	72155	72010	65435	3	65774	50010	40020	10000	70020	10000	72037	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10939	2	146	504	10707	263	13	929	76	74	11061	118	51	119	3	0	4	0	0	2520	0	7	65	13	7	71813	40672	852	944	1054	10000	40010	72066	72006	72058	72065	72211
50024	72096	539	1	0	0	0	0	0	762	0	811	1	712	1	128	72088	829	40	17	71769	25	50885	40658	10159	40010	10000	632834	2726453	0	49	68857	72403	72006	65493	3	65805	50010	40020	10000	70020	10000	72110	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10916	3	134	495	10703	265	9	898	80	73	10952	123	32	134	2	0	3	0	0	2520	0	7	65	7	14	71975	40620	1000	928	1066	10000	40010	72191	72088	72126	72257	71941
50024	72031	540	1	0	0	0	0	0	617	0	840	1	720	2	120	71976	810	35	15	72093	25	50820	40690	10178	40010	10000	613881	2747019	1	49	68748	71762	72203	65319	3	65811	50010	40020	10000	70020	10000	71826	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10907	1	138	516	10687	277	10	904	78	66	10966	119	46	134	1	4	4	0	0	2520	0	8	85	7	5	72013	40664	924	818	856	10000	40010	71898	71892	71945	72073	72071
50024	72258	540	2	0	2	0	0	0	568	0	805	1	752	1	92	71944	798	36	21	71976	25	50830	40646	10173	40010	10000	633939	2735049	0	49	68895	71794	72092	65418	14	65822	50010	40020	10000	70020	10000	71947	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10940	4	141	494	10686	278	9	906	66	71	10937	131	39	129	1	0	3	0	0	2520	0	7	85	6	8	72083	40656	920	992	914	10000	40010	72067	72122	72143	72094	72258
50024	71952	540	2	0	1	0	0	0	675	0	797	1	728	1	140	72137	777	45	16	71909	25	50810	40730	10162	40010	10000	633445	2730387	1	49	69160	72229	72052	65740	3	65769	50010	40020	10000	70020	10000	72015	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10925	4	153	485	10697	291	9	937	66	81	10972	117	43	132	2	1	3	0	0	2520	0	12	65	7	6	71954	40636	848	940	918	10000	40010	72034	72131	71939	72211	71954
50024	72125	538	1	0	0	0	0	0	677	0	799	1	720	1	124	72163	792	41	16	71810	25	50805	40714	10168	40010	10000	631984	2729092	1	49	68934	72064	72042	65460	3	65706	50010	40020	10000	70020	10000	71989	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10927	4	172	513	10677	260	13	949	72	78	11001	121	41	124	2	0	7	1	0	2520	0	7	85	7	6	71854	40644	986	938	918	10000	40010	72083	72127	71967	72141	71875
50024	72150	539	0	0	0	0	0	0	619	0	815	1	680	2	108	72026	821	33	16	71751	25	50875	40698	10154	40010	10000	612849	2734296	0	49	69001	72232	72294	65473	3	65813	50010	40020	10000	70020	10000	72138	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10889	0	150	518	10689	269	9	908	44	66	10959	125	39	133	0	0	9	0	0	2520	0	8	85	7	5	71918	40668	1016	902	1012	10000	40010	72183	72128	72195	72037	72218
50024	72343	539	2	0	2	0	0	0	597	0	806	1	712	1	128	72111	829	35	18	71800	25	50785	40682	10173	40010	10000	633302	2726077	1	49	69229	72019	72015	65840	3	65634	50010	40020	10000	70020	10000	71968	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10926	1	131	508	10676	261	11	904	48	68	10969	129	37	118	1	4	3	0	1	2520	0	7	65	7	4	72144	40704	860	944	882	10000	40010	72236	72109	71957	72299	72097
50024	71909	541	2	0	0	0	0	0	766	0	817	1	688	3	104	72087	794	39	13	72048	25	50900	40638	10174	40010	10000	614848	2721942	1	49	69049	72020	72194	65619	3	65841	50010	40020	10000	70020	10000	72066	35	1	1	40022	10	9	10	10000	30010	10000	0	10	10908	2	168	517	10678	259	6	963	76	85	10975	126	57	138	2	0	3	0	0	2520	0	5	85	5	7	71843	40628	874	853	950	10000	40010	72100	72141	72086	72193	72104

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6], #8
  ldrb w0, [x7], #8
  ldrb w0, [x8], #8
  ldrb w0, [x9], #8
  ldrb w0, [x10], #8
  ldrb w0, [x11], #8
  ldrb w0, [x12], #8
  ldrb w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3636

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29773	218	3	0	0	0	0	0	6314	827	1	688	90	116	29160	759	368	1933	2144	1820	25	160149	80161	80000	80100	80000	400753	1286809	0	61	49	25920	29176	29041	8858	3	9164	160100	80200	80000	80200	80000	28834	35	1	1	80201	100	99	3	100	80000	100	80000	100	80922	32	376	4696	0	85011	681	15	899	32	5075	84645	775	129	4449	4713	14	0	4	0	5110	1	16	1	1	29265	25	80058	398	394	75	80000	80100	28846	29097	28976	29271	29080
160204	29109	218	2	0	0	0	0	0	6482	837	1	736	90	168	29207	768	295	1773	1947	1899	25	160141	80162	80000	80100	80000	400799	1279704	1	67	49	26042	28970	29200	8660	3	8927	160100	80200	80000	80200	80000	28927	35	1	1	80201	100	99	7	100	80000	100	80000	100	80900	32	357	4492	0	84194	705	9	867	32	4768	85319	805	126	4844	4769	33	3	5	0	5110	1	16	1	1	29126	30	80054	323	283	88	80000	80100	29057	28878	29171	29046	29094
160204	29021	218	2	0	0	0	0	0	6651	808	1	584	88	132	29123	767	361	2120	1854	1792	25	160154	80146	80000	80100	80000	400770	1284127	0	64	49	25981	29042	29165	9163	3	9186	160100	80200	80000	80200	80000	28968	35	2	1	80201	100	99	8	100	80000	100	80000	100	80920	55	405	5395	0	84918	705	12	898	36	4687	85914	673	114	4855	4650	51	3	0	0	5110	1	16	1	1	28872	21	80061	361	291	85	80000	80100	29235	28894	28878	29035	29084
160204	29197	219	2	0	0	0	0	0	6314	779	1	688	113	136	29078	741	363	1944	2100	1786	25	160167	80169	80000	80100	80000	400745	1282412	0	47	49	25991	29069	29295	8880	3	9171	160100	80200	80000	80200	80000	29020	35	1	1	80201	100	99	9	100	80000	100	80000	100	80938	53	390	4997	0	84862	735	12	863	36	5785	85639	663	132	4605	4399	55	1	0	0	5110	1	16	1	1	29023	24	80066	418	361	103	80000	80100	28905	29192	29085	29127	28846
160204	29050	218	2	0	0	0	0	0	6876	831	1	720	107	92	29161	730	312	1987	2130	1886	25	160151	80143	80000	80100	80000	400778	1285856	0	74	49	25833	28958	29158	9094	3	9220	160100	80200	80000	80200	80000	29123	35	1	1	80201	100	99	14	100	80000	100	80000	100	80865	16	392	4726	0	85335	714	10	868	56	5326	85577	685	123	4735	4308	35	0	5	0	5110	1	16	1	1	28994	44	80064	318	296	79	80000	80100	29174	29121	29152	29136	28932
160204	29154	217	2	0	0	2	0	0	6653	779	1	576	84	224	29146	783	337	1744	2035	1853	25	160159	80155	80000	80100	80000	400766	1278489	0	50	49	26275	28946	29377	9061	3	9260	160100	80200	80000	80200	80000	29325	35	1	1	80201	100	99	16	100	80000	100	80000	100	80916	38	426	4792	0	84890	697	8	878	32	4705	85681	791	112	4550	4251	31	0	0	0	5110	1	17	1	1	29071	44	80048	312	310	90	80000	80100	29113	29133	29099	29293	29440
160204	29094	218	3	0	0	0	0	0	6643	768	1	720	98	128	29134	764	363	1692	2171	1709	25	160167	80163	80000	80100	80000	400752	1278256	0	57	49	26073	28963	29231	9218	3	9057	160100	80200	80000	80200	80000	29261	35	1	1	80201	100	99	9	100	80000	100	80000	100	80898	34	406	5578	0	84792	704	11	832	72	4950	85660	717	124	4835	4436	36	2	8	0	5110	1	16	1	1	29218	25	80054	378	375	82	80000	80100	29087	28840	29171	29003	29106
160204	29289	220	2	2	0	0	0	0	6311	820	1	640	89	236	28945	778	361	1982	2067	1925	25	160140	80149	80000	80100	80000	400767	1283663	0	44	49	25970	29486	28946	9212	3	8851	160100	80200	80000	80200	80000	29284	35	1	1	80201	100	99	13	100	80000	100	80000	100	80845	33	354	5213	0	85190	696	10	846	38	5141	85686	739	124	4298	4863	34	0	3	0	5110	1	16	1	1	29144	33	80054	357	312	92	80000	80100	29043	28926	29006	29195	29189
160204	29073	218	2	2	0	2	0	0	6035	765	1	688	96	136	29154	746	353	1877	2288	1627	25	160158	80163	80000	80100	80000	400786	1277583	0	57	49	26259	29230	29052	9249	3	8863	160100	80200	80000	80200	80000	29327	35	1	1	80201	100	99	12	100	80000	100	80000	100	80871	37	345	5198	0	84422	683	10	845	28	4798	85545	717	117	4667	5208	35	3	5	0	5110	1	16	1	1	29316	30	80060	306	313	97	80000	80100	29074	28951	28811	29049	28705
160204	29096	217	2	2	0	2	0	0	6278	762	1	672	101	124	28965	760	357	2160	1904	1673	25	160147	80158	80000	80100	80000	400777	1288465	0	63	49	26109	29046	29171	9057	3	8988	160100	80200	80000	80200	80000	29123	35	1	1	80201	100	99	7	100	80000	100	80000	100	80932	38	408	5324	0	84934	642	14	886	28	4354	86078	764	128	4796	4516	17	4	3	0	5110	1	17	1	1	29311	29	80064	273	333	75	80000	80100	28958	28929	29078	29070	29250

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3670

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29701	223	2	0	3	1	1	0	0	6970	776	1	688	108	136	29677	801	363	1783	1788	2161	25	160080	80070	80000	80010	80000	400398	1301856	1	76	49	26241	29368	29359	9177	0	3	9274	160010	80020	80000	80020	80000	29407	35	1	1	80021	10	9	24	10	80000	10	80000	10	80974	79	408	6366	85406	628	10	912	34	5104	85794	814	128	4960	5038	51	3	4	5020	5	16	6	4	29433	31	80060	529	522	103	80000	80010	29215	29231	29355	29203	29283
160024	29430	218	4	0	0	1	1	0	0	6560	848	1	696	94	128	29341	746	289	1829	1976	2140	25	160071	80086	80000	80010	80000	400326	1284265	1	59	49	26165	29449	29495	9409	0	3	9263	160010	80020	80000	80020	80000	29406	35	2	1	80021	10	9	28	10	80000	10	80000	10	80928	72	424	5830	85344	645	13	898	76	5435	85944	855	136	5514	5189	52	0	3	5020	5	16	2	4	29126	30	80060	506	533	97	80000	80010	29433	29283	29225	29320	29453
160024	29359	220	4	4	0	1	1	0	0	6733	809	1	744	93	108	29311	780	331	1752	1706	2121	25	160064	80076	80000	80010	80000	400392	1294130	1	57	49	26340	29490	29283	9164	0	3	9297	160010	80020	80000	80020	80000	29326	35	1	1	80021	10	9	45	10	80000	10	80000	10	80919	60	393	5373	85734	657	14	902	28	5159	85712	820	122	5373	5260	33	0	12	5020	5	16	2	4	29426	48	80058	542	571	111	80000	80010	29350	29360	29525	29226	29553
160024	29171	219	4	0	0	1	1	0	0	6379	798	1	744	99	144	29303	801	280	1877	1774	2036	25	160071	80066	80000	80010	80000	400364	1297466	1	70	49	26145	29392	29574	9462	0	3	9407	160010	80020	80000	80020	80000	29217	35	1	1	80021	10	9	33	10	80000	10	80000	10	80898	43	378	5750	85893	667	12	919	116	5307	86041	823	131	4807	5058	18	0	3	5020	3	16	5	5	29342	18	80062	540	541	95	80000	80010	29318	29474	29454	29570	29429
160024	29469	221	4	0	0	1	0	0	0	6742	802	1	744	87	112	29556	780	332	1975	1805	2012	25	160057	80064	80000	80010	80000	400340	1290623	1	72	49	26510	29491	29449	9133	0	3	9537	160010	80020	80000	80020	80000	29103	35	1	1	80021	10	9	28	10	80000	10	80000	10	80911	69	397	5477	85285	663	12	878	68	5275	85946	748	129	4397	4549	70	0	4	5020	3	16	2	4	29291	26	80056	561	535	95	80000	80010	29398	29462	29275	29322	29429
160024	29370	219	4	0	0	1	0	0	0	6704	850	1	712	111	148	29244	803	353	1702	1827	2272	25	160077	80073	80000	80010	80000	400356	1295621	1	76	49	26293	29351	29481	9483	0	3	9458	160010	80020	80000	80020	80000	29403	35	1	1	80021	10	9	28	10	80000	10	80000	10	80936	45	424	5129	85204	682	10	863	52	5120	85795	819	130	4793	4883	70	0	0	5020	4	16	2	4	29444	30	80059	549	501	102	80000	80010	29469	29224	29461	29577	29511
160024	29230	221	4	0	0	1	0	0	0	6628	803	1	704	106	148	29256	794	298	1875	1898	2014	25	160075	80074	80000	80010	80000	400323	1300659	1	62	49	26498	29438	29257	9320	0	3	9309	160010	80020	80000	80020	80000	29242	35	1	1	80021	10	9	39	10	80000	10	80000	10	80911	65	366	5957	85415	655	14	872	38	4897	85795	708	131	4753	5087	46	0	3	5020	4	16	3	6	29346	25	80066	567	514	102	80000	80010	29238	29493	29135	29528	29552
160024	29463	221	4	0	0	1	0	0	0	6496	769	1	752	96	156	29413	795	342	1747	1900	2101	25	160069	80065	80000	80010	80000	400397	1297765	1	69	49	26336	29262	29366	9398	0	3	9030	160010	80020	80000	80020	80000	29247	35	1	1	80021	10	9	25	10	80000	10	80000	10	80948	51	367	5511	85641	661	11	893	40	5443	86863	823	127	4798	4834	51	3	3	5020	4	16	4	2	29135	27	80061	524	537	118	80000	80010	29183	29474	29245	29509	29228
160024	29461	219	4	0	1	1	0	0	0	6511	792	1	720	97	96	29350	780	324	1637	1942	2135	25	160056	80067	80000	80010	80000	400365	1305153	1	71	49	26117	29158	29168	9269	0	3	9288	160010	80020	80000	80020	80000	29277	35	1	1	80021	10	9	26	10	80000	10	80000	10	80993	42	363	5528	85594	699	13	888	32	5635	85993	783	128	5111	4861	63	0	3	5020	4	16	4	3	29232	31	80059	535	524	97	80000	80010	29419	29459	29411	29426	29303
160024	29444	220	4	0	0	1	1	0	0	6323	764	1	688	121	144	29551	783	334	2290	1808	2052	25	160074	80084	80000	80010	80000	400366	1287903	1	58	49	26460	29261	29164	9350	0	3	9296	160010	80020	80000	80020	80000	29214	35	1	1	80021	10	9	27	10	80000	10	80000	10	80973	71	386	5658	84800	649	9	878	26	5634	85800	832	127	4692	4950	52	0	6	5020	6	16	4	2	29215	17	80059	517	541	96	80000	80010	29472	29495	29338	29315	29360

LDRB (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations