Firestorm: PRFM (register, PLDL3KEEP) measurements

Code:

  prfm pldl3keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1612	12	0	30	15	29	2396	1620	876	25	1000	1000	1000	70049	1	1599	1619	1305	3	1427	1000	1000	1000	1565	1585	1	1	1001	284	2235	2245	3214	0	2367	2215	1000	73	2	16	2	2	1507	1000	1628	1618	1615	1631	1671
1004	1621	12	0	30	15	30	2366	1608	904	25	1000	1000	1000	69462	1	1601	1634	1329	3	1490	1000	1000	1000	1599	1621	1	1	1001	266	2226	2236	3228	0	2396	2233	1000	73	2	16	2	2	1516	1000	1583	1596	1569	1617	1589
1004	1618	12	0	31	15	30	2412	1600	895	25	1000	1000	1000	70045	1	1599	1659	1297	3	1425	1000	1000	1000	1581	1596	1	1	1001	253	2218	2198	3244	0	2393	2229	1000	73	2	16	2	2	1542	1000	1627	1623	1627	1593	1618
1004	1631	12	0	29	15	29	2509	1608	926	25	1000	1000	1000	70229	1	1603	1620	1351	3	1440	1000	1000	1000	1583	1606	1	1	1001	233	2246	2248	3215	0	2395	2236	1000	73	2	16	2	2	1516	1000	1613	1620	1614	1595	1595
1004	1634	12	0	29	15	30	2402	1608	892	25	1000	1000	1000	70216	1	1593	1595	1310	3	1484	1000	1000	1000	1598	1595	1	1	1001	275	2241	2240	3227	0	2390	2243	1000	73	2	16	2	2	1516	1000	1575	1616	1632	1620	1613
1004	1606	12	0	30	15	31	2395	1634	887	25	1000	1000	1000	71004	1	1594	1587	1305	3	1439	1000	1000	1000	1583	1635	1	1	1001	238	2211	2210	3208	0	2407	2229	1000	73	2	16	2	2	1499	1000	1595	1609	1625	1582	1640
1004	1624	12	0	30	15	29	2396	1585	897	25	1000	1000	1000	70935	1	1602	1634	1300	3	1460	1000	1000	1000	1622	1588	1	1	1001	266	2233	2193	3211	0	2391	2238	1000	73	2	16	2	2	1506	1000	1594	1567	1650	1624	1618
1004	1634	12	0	30	15	31	2405	1592	930	25	1000	1000	1000	70656	1	1588	1568	1353	3	1478	1000	1000	1000	1595	1593	1	1	1001	259	2238	2210	3225	0	2391	2251	1000	73	2	16	2	2	1494	1000	1584	1611	1623	1591	1632
1004	1631	12	0	30	15	30	2411	1578	880	25	1000	1000	1000	69889	1	1580	1671	1297	3	1471	1000	1000	1000	1580	1589	1	1	1001	245	2225	2197	3224	0	2396	2228	1000	73	2	16	2	2	1485	1000	1615	1620	1626	1624	1625
1004	1608	12	0	30	15	30	2398	1601	896	25	1000	1000	1000	70007	1	1605	1630	1310	3	1463	1000	1000	1000	1594	1582	1	1	1001	259	2228	2246	3222	0	2414	2223	1000	73	2	16	2	2	1497	1000	1642	1631	1612	1623	1624

Test 2: throughput

Code:

  prfm pldl3keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5627

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15514	117	371	193	368	24731	15530	9552	25	20205	10199	10000	10100	10000	130387	731969	1	37	49	12466	15713	15655	12847	3	13061	20100	10200	10000	10200	10000	15601	155	1	1	20201	100	99	2215	100	10100	100	23013	23189	32916	24636	23055	10000	1310	1	17	1	1	15452	10108	10000	10100	15615	15664	15665	15581	15608
20204	15586	117	358	200	366	24623	15657	9706	25	20190	10205	10000	10100	10000	130141	730098	1	44	49	12627	15571	15675	12917	3	13120	20100	10200	10000	10200	10000	15567	155	1	1	20201	100	99	2260	100	10100	100	22971	22756	33225	24694	23025	10000	1310	1	17	1	1	15461	10102	10000	10100	15635	15669	15569	15556	15667
20204	15653	116	358	192	364	24684	15601	9696	25	20229	10211	10000	10100	10000	130876	728815	1	34	49	12713	15672	15595	13047	3	12988	20100	10200	10000	10200	10000	15597	154	1	1	20201	100	99	2176	100	10100	100	23047	22927	33106	24729	22993	10000	1310	1	16	1	1	15443	10126	10000	10100	15519	15655	15571	15731	15704
20204	15540	117	371	196	360	24811	15506	9636	25	20211	10226	10000	10100	10000	131139	727781	1	42	49	12427	15517	15544	12841	3	13039	20100	10200	10000	10200	10000	15519	155	1	1	20201	100	99	2257	100	10100	100	23002	22839	32728	24692	23012	10000	1310	1	16	1	1	15486	10081	10000	10100	15662	15754	15678	15537	15627
20204	15685	117	366	195	369	24481	15556	9628	25	20193	10223	10000	10100	10000	130258	737739	1	29	49	12668	15697	15547	12847	3	12967	20100	10200	10000	10200	10000	15617	154	1	1	20201	100	99	2286	100	10100	100	22835	22906	32953	24594	23290	10000	1310	1	16	1	1	15517	10117	10000	10100	15550	15625	15615	15655	15602
20204	15590	117	365	193	364	24749	15527	9692	25	20220	10214	10000	10100	10104	129945	731587	1	38	49	12547	15633	15592	12779	3	13146	20100	10200	10000	10200	10000	15632	156	1	1	20201	100	99	2151	100	10100	100	23137	22903	33025	24713	23189	10000	1310	1	16	1	1	15454	10129	10000	10100	15733	15632	15562	15630	15671
20204	15677	117	358	194	368	24831	15554	9659	25	20199	10206	10000	10100	10000	130432	728400	1	33	49	12586	15720	15616	13035	3	13059	20100	10200	10000	10200	10000	15685	156	1	1	20201	100	99	2212	100	10100	100	22962	22909	33161	24571	23069	10000	1344	1	17	1	1	15461	10117	10000	10100	15536	15595	15686	15703	15567
20204	15624	117	360	197	361	24736	15544	9643	25	20208	10217	10000	10100	10000	131292	731563	1	34	49	12411	15578	15593	12863	3	13207	20100	10200	10000	10200	10000	15659	155	1	1	20201	100	99	2193	100	10100	100	23079	23055	33063	24782	23152	10000	1310	1	16	1	1	15478	10144	10000	10100	15655	15481	15661	15558	15692
20204	15686	117	362	189	363	24793	15679	9650	25	20196	10211	10000	10100	10000	130038	723943	1	40	49	12519	15649	15500	12878	3	13096	20100	10200	10000	10200	10000	15553	155	1	1	20201	100	99	2233	100	10100	100	23042	23008	32979	24586	22902	10000	1311	1	16	1	1	15410	10141	10000	10100	15584	15499	15607	15645	15584
20204	15647	118	374	189	369	24707	15716	9732	25	20199	10217	10000	10100	10000	130856	734153	1	28	49	12474	15504	15676	12932	3	13001	20100	10200	10000	10200	10000	15580	156	1	1	20201	100	99	2260	100	10100	100	23061	22940	33018	24793	22936	10000	1310	1	16	1	1	15586	10120	10000	10100	15438	15657	15631	15456	15630

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5598

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	bb	l1d tlb miss nonspec (c1)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15617	117	379	191	376	24802	15648	9725	25	20154	10133	10000	10010	10000	130712	738969	0	48	49	12582	15531	15604	12788	3	13068	20010	10020	10000	10020	10000	15591	143	1	1	20021	10	9	2219	10	10010	10	23148	23078	33411	24885	23345	10000	0	1270	1	16	1	1	15402	10114	10000	10010	15501	15533	15505	15637	15835
20024	15527	117	372	199	368	24887	15630	9576	25	20163	10142	10000	10010	10000	131817	734531	1	31	49	12412	15716	15668	12886	3	13055	20010	10020	10000	10020	10000	15619	143	1	1	20021	10	9	2168	10	10010	10	23251	23035	33016	24974	23106	10000	0	1270	1	16	1	1	15477	10144	10000	10010	15619	15635	15632	15724	15560
20024	15775	117	375	196	372	25065	15556	9722	25	20127	10166	10000	10010	10000	132665	729413	1	33	49	12566	15609	15525	12877	3	13156	20010	10020	10000	10020	10000	15572	150	1	1	20021	10	9	2126	10	10010	10	23295	23055	33028	24839	23385	10000	0	1270	1	16	2	1	15478	10144	10000	10010	15589	15568	15603	15668	15514
20024	15603	116	372	197	371	24732	15527	9609	25	20175	10130	10000	10010	10000	132326	730976	0	48	49	12439	15668	15641	12931	3	13027	20010	10020	10000	10020	10000	15439	142	1	1	20021	10	9	2217	10	10010	10	23248	23213	33026	24815	23327	10000	0	1270	1	16	1	1	15524	10132	10000	10010	15511	15565	15719	15610	15612
20024	15500	117	372	196	380	24741	15567	9625	25	20157	10124	10000	10010	10000	132930	731322	0	47	49	12473	15534	15845	12879	3	13232	20010	10020	10000	10020	10000	15589	150	1	1	20021	10	9	2258	10	10010	10	23076	23180	32990	24652	23227	10000	0	1270	1	16	1	1	15496	10108	10000	10010	15448	15558	15622	15502	15598
20024	15423	116	372	194	369	25037	15579	9570	25	20142	10160	10000	10010	10000	130703	732883	1	39	49	12581	15561	15572	12959	3	13094	20010	10020	10000	10020	10000	15707	143	1	1	20021	10	9	2313	10	10010	10	23069	23218	33087	24886	23167	10000	0	1271	1	16	1	1	15406	10138	10000	10010	15589	15639	15607	15447	15676
20024	15551	117	368	200	374	24770	15633	9664	25	20136	10121	10000	10010	10000	130854	728333	1	35	49	12460	15639	15562	12928	3	13063	20010	10020	10000	10020	10000	15504	143	1	1	20021	10	9	2248	10	10010	10	23124	23143	33148	24839	23037	10000	0	1271	1	16	1	1	15437	10141	10000	10010	15639	15660	15706	15726	15577
20024	15650	116	375	191	371	24760	15625	9487	25	20142	10154	10000	10010	10000	130267	730433	0	34	49	12583	15564	15575	12911	3	13058	20010	10020	10000	10020	10000	15616	144	1	1	20021	10	9	2176	10	10010	10	23107	23234	33123	24657	22989	10000	0	1270	1	16	1	1	15512	10126	10000	10010	15635	15525	15592	15561	15786
20024	15579	116	372	197	372	24834	15621	9527	25	20136	10187	10000	10010	10000	131413	726636	0	50	49	12565	15527	15577	12845	3	13054	20010	10020	10000	10020	10000	15608	149	1	1	20021	10	9	2203	10	10010	10	23042	23200	32969	24655	23143	10000	0	1270	1	16	1	1	15434	10096	10000	10010	15554	15642	15686	15531	15647
20024	15728	117	379	197	373	24884	15568	9670	25	20151	10139	10000	10010	10000	129684	730767	0	43	49	12611	15467	15560	12897	3	13289	20010	10020	10000	10020	10000	15553	143	1	1	20021	10	9	2202	10	10010	10	22873	23188	33267	24727	23032	10000	0	1270	2	16	1	2	15565	10126	10000	10010	15664	15684	15593	15718	15455

Test 3: throughput

Code:

  prfm pldl3keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5423

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	map dispatch bubble (d6)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15448	117	306	156	307	24315	15431	9483	25	10100	100	10000	100	10000	500	724753	1	49	12347	15454	15387	13920	6	14203	10100	200	10008	200	10008	15299	12203	1	1	10201	100	99	2552	100	100	100	22437	22532	32485	0	24253	22517	10000	0	1	1	1	717	0	0	16	15366	10000	100	15430	15514	15408	15435	15403
10204	15474	115	306	153	305	24351	15401	9472	25	10100	100	10000	100	10000	500	722495	1	49	12342	15375	15416	14027	7	14089	10100	200	10016	200	10008	15383	12201	1	1	10201	100	99	2463	100	100	100	22510	22486	32439	0	24261	22582	10000	0	1	1	1	718	0	0	16	15203	10000	100	15353	15384	15386	15381	15404
10204	15384	115	310	156	304	24250	15392	9457	25	10100	100	10000	100	10000	500	720573	0	49	12360	15426	15337	14012	7	14123	10100	200	10008	200	10008	15398	12161	1	1	10201	100	99	2530	100	100	100	22443	22420	32475	0	24225	22428	10000	0	1	1	1	717	0	0	16	15335	10000	100	15432	15407	15382	15457	15383
10204	15440	116	310	154	303	24234	15314	9511	25	10100	100	10000	100	10000	500	722408	0	49	12296	15361	15402	14003	6	14143	10100	200	10016	200	10016	15457	12161	1	1	10201	100	99	2493	100	100	100	22557	22476	32465	0	24286	22531	10000	0	1	1	1	717	0	0	16	15273	10000	100	15382	15439	15382	15483	15368
10204	15386	115	307	153	309	24273	15367	9461	25	10100	100	10000	100	10119	500	726611	0	49	12332	15462	15550	13968	7	14053	10100	200	10016	200	10008	15394	12203	1	1	10201	100	99	2585	100	100	100	22547	22480	32468	0	24256	22510	10000	0	1	1	1	719	0	0	16	15280	10000	100	15428	15390	15441	15383	15368
10204	15467	116	312	157	308	24265	15336	9520	25	10100	100	10000	100	10001	500	723195	0	49	12322	15476	15370	14070	7	14120	10100	200	10008	200	10008	15330	12194	1	1	10201	100	99	2576	100	100	100	22547	22482	32468	0	24247	22535	10000	0	1	1	1	717	0	0	16	15296	10000	100	15428	15388	15470	15383	15454
10204	15467	115	310	154	306	24373	15407	9524	25	10100	100	10000	100	10000	500	723287	0	49	12306	15369	15476	14012	7	14123	10100	200	10008	200	10008	15422	12166	1	1	10201	100	99	2530	100	100	100	22582	22477	32567	0	24225	22491	10000	0	1	1	1	717	0	0	16	15242	10000	100	15423	15407	15361	15418	15426
10204	15420	116	308	156	304	24288	15435	9468	25	10100	100	10000	100	10000	500	722146	0	49	12421	15459	15329	13946	7	14170	10100	200	10016	200	10016	15411	12221	1	1	10201	100	99	2562	100	100	100	22500	22519	32458	0	24256	22499	10000	0	1	1	1	719	0	0	16	15320	10000	100	15391	15487	15408	15466	15482
10204	15474	116	305	152	307	24317	15420	9342	25	10100	100	10000	100	10000	500	722494	0	49	12305	15381	15349	13981	7	14125	10107	200	10008	200	10008	15338	12135	1	1	10201	100	99	2451	100	100	100	22414	22467	32409	0	24188	22517	10000	0	1	1	1	718	0	0	16	15291	10000	100	15409	15411	15405	15358	15391
10204	15414	115	308	152	304	24375	15461	9514	25	10100	100	10000	100	10003	500	718697	0	49	12313	15427	15393	13952	6	14144	10100	200	10008	200	10008	15378	12190	1	1	10201	100	99	2562	100	100	100	22523	22559	32525	0	24237	22543	10000	0	1	1	1	737	0	0	16	15188	10000	100	15438	15379	15434	15433	15414

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15434	116	294	146	294	0	23927	15483	9575	25	10010	10	10000	10	10000	50	722507	0	49	12431	15465	15449	14039	3	14204	10010	20	10000	20	10000	15436	15446	1	1	10021	10	9	2544	10	10	10	22170	22211	32136	0	0	23865	22201	10000	0	640	2	16	2	2	15372	10000	10	15503	15471	15457	15515	15590
10024	15483	116	291	147	292	0	23924	15496	9516	25	10010	10	10000	10	10000	50	726140	0	49	12391	15476	15504	14042	3	14238	10010	20	10000	20	10000	15418	15511	1	1	10021	10	9	2596	10	10	10	22189	22211	32220	0	0	23955	22249	10000	0	640	2	16	2	2	15327	10000	10	15460	15533	15506	15468	15481
10024	15493	116	294	148	290	0	23916	15407	9553	25	10010	10	10000	10	10000	50	722021	0	49	12473	15532	15424	14000	3	14232	10010	20	10000	20	10000	15376	15454	1	1	10021	10	9	2563	10	10	10	22132	22174	32199	0	0	23874	22192	10000	0	640	2	16	2	2	15377	10000	10	15544	15454	15526	15498	15447
10024	15564	116	290	145	294	0	23914	15568	9573	25	10010	10	10000	10	10000	50	722225	0	49	12427	15448	15469	14133	3	14200	10010	20	10000	20	10000	15460	15428	1	1	10021	10	9	2493	10	10	10	22168	22242	32238	0	0	23823	22236	10000	0	640	2	16	2	2	15346	10000	10	15448	15486	15474	15443	15420
10024	15415	116	295	147	290	0	23935	15510	9583	25	10010	10	10000	10	10000	50	727241	1	49	12408	15464	15544	14084	3	14145	10010	20	10000	20	10000	15412	15397	1	1	10021	10	9	2578	10	10	10	22203	22219	32219	0	0	23890	22218	10000	0	640	2	16	2	2	15363	10000	10	15419	15441	15488	15466	15517
10024	15464	116	294	145	292	0	23943	15449	9552	25	10010	10	10000	10	10000	50	724147	0	49	12416	15417	15426	14168	3	14264	10010	20	10000	20	10000	15499	15413	1	1	10021	10	9	2576	10	10	10	22211	22291	32220	0	0	23899	22163	10000	0	640	2	16	2	2	15358	10000	10	15398	15489	15536	15520	15526
10024	15532	116	290	148	295	0	23893	15513	9479	25	10010	10	10000	10	10000	50	726314	0	49	12390	15470	15532	14023	3	14234	10010	20	10000	20	10000	15439	15382	1	1	10021	10	9	2553	10	10	10	22219	22212	32132	0	0	23936	22093	10000	0	640	2	16	2	2	15348	10000	10	15426	15404	15584	15453	15488
10024	15410	116	290	147	294	0	23892	15464	9527	25	10010	10	10000	10	10104	61	732996	0	49	12390	15464	15489	14076	3	14183	10010	22	10226	22	10121	15447	15534	2	1	10021	10	9	2596	10	10	10	22230	22347	32253	2	0	24125	22363	10000	4	640	2	16	2	2	15384	10000	10	15491	15467	15699	15508	15531
10024	15736	115	295	147	294	0	23917	15479	9559	25	10010	10	10000	10	10000	50	725757	0	49	12383	15537	15477	14177	3	14153	10010	20	10000	20	10000	15443	15524	1	1	10021	10	9	2544	10	10	10	22157	22185	32188	0	0	23874	22267	10000	0	640	2	16	2	2	15377	10000	10	15452	15552	15446	15459	15485
10024	15518	116	292	146	291	0	23952	15591	9559	25	10010	10	10000	10	10000	50	722858	0	49	12393	15556	15520	14105	3	14335	10010	20	10000	20	10000	15518	15477	1	1	10021	10	9	2589	10	10	10	22213	22207	32222	0	0	23850	22218	10000	0	640	2	16	2	2	15312	10000	10	15503	15466	15451	15528	15465

PRFM (register, PLDL3KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations