Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MVN (register, lsr, 32-bit)

Test 1: uops

Code:

  mvn w0, w0, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)acc3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
10042035150611000173525200020001000325701203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
100420351506110001735252000200010003257002035203515753184210001000100020354211100110002600731671117812000100020362036203620362036
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036
10042035150611000173525200020001000325700203520351575318421000100010002035421110011000000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  mvn w0, w0, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351503611000019803252010020100101111849850491695520035200351847771873610111102321023220035421110201100991001010010000111720016001984520000101002003620036200362003620036
10204200351500611000019803252010020100101111849851491695520035200351847771873510111102321023220035421110201100991001010010000111720016001984520000101002003620036200362003620036
10204200351500611000019803252010020100101111849851491695520035200351847771873510111102321023220035421110201100991001010010000111720016001984520000101002003620036200362003620036
10204200351500611000019803252010020100101111849850491695520035200351847771873510111102321023220035421110201100991001010010020111720016001984520000101002003620036200362003620036
10204200351500611000019803252010020100101111849850491695520035200351847731870010100102001020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
1020420035150425621000019803252010020100101001853420491695520035200351842931870010100102001020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515027611000019803252010020100101001853420491695520035200351842931870010100102001020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
10204200351506611000019803252010020100101001853420491695520035200351842931870010100102001020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
10204200351500611000019803252010020100101001853420491695520035200351842931870010100102001020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515012611000019803252010020100101001853420491695520035200351842931870010100102001020020035421110201100991001010010000000710159111979120000101002003620036200362003620081

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500000021300821000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463441979220000100102003620036200362003620036
100242003515000000300611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463341979220000100102003620036200362003620036
100242003515000000000611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463441979220000100102003620036200362003620036
1002420035150000008100821000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463441979220000100102003620036200362003620036
1002420035150000001800611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463341979220000100102003620036200362003620036
100242003515000000000611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640363431979220000100102003620036200362003620036
1002420035150000007500611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463441979220000100102003620036200362003620036
100242003515000000900611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640363341979220000100102003620036200362003620036
10024200351500000026700611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463441979220000100102003620036200362003620036
100242003515000000000611000019743252001020010100101853104916955200352003518451318718100101002010020200354211100211091010010100000000640463341979220000100102003620036200362003620036

Test 3: throughput

Count: 8

Code:

  mvn w0, w8, lsr #17
  mvn w1, w8, lsr #17
  mvn w2, w8, lsr #17
  mvn w3, w8, lsr #17
  mvn w4, w8, lsr #17
  mvn w5, w8, lsr #17
  mvn w6, w8, lsr #17
  mvn w7, w8, lsr #17
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3344

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267682000000003300288003126146281601821601828026216190604923652267322673216651816661802628037680376267323911802011009910080100100000000011151290160026729160082801002673326733267332673326733
802042673220000000041400288003126146281601821601828026216190604923652267322673116651816661802628037680376267323911802011009910080100100000000011151290160026729160082801002673226733267332673326733
80204267322010000001500288003126146281601821601828026216190604923652267322673216651816661802628037680376267323911802011009910080100100000000011151290160026729160082801002673326733267332673326733
8020426732200000000000288003126146281601821601828026216190604923652267322673216651816661802628037680376267323911802011009910080100100000000011151290160026729160082801002673326733267332673326733
8020426732200000000000288003126146281601821601828026216190604923651267322673216651816661802628037680376267323911802011009910080100100000000011151290160026728160082801002673326733267332673326733
8020426732200000000300498003126146281601821601828026216190604923652267322673216651816661802628037680376267323911802011009910080100100000000011151290160026729160082801002673326733267332673226733
8020426732200000000300288003126146281601821601828026216190604923651267322673216651716661802628037680376267323911802011009910080100100000000011151290160026729160082801002673326733267332673326733
80204267322000000001500288003126146281601821601828026216190604923652267322673216651816661802628037680376267323911802011009910080100100000000011151290160026729160082801002673326733267322673326733
8020426732200000000000288003126146281601821601828026216190604923652267312673216651816661802628037680376267323911802011009910080100100000000011151290160026729160082801002673326733267332673326733
8020426732200000000000288003126146281601821601828026216190604923652267322673216651816661802628060080376267873911802011009910080100100000000011151290160026729160082801002673326733267332673326733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfl1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267342000000000300061800002128025160010160010800101631420492363126711267111662331668580010800208002026711391180021109108001010000000000502001722161626704160000800102671226712267122671226712
800242671120000000000006180000212802516001016001080010163142049236312671126711166233166858001080020800202671139118002110910800101000000000050200162271626704160000800102671226712267122671226712
800242671120000000000006180000212802516001016001080010163142049236312671126711166233166858001080416800202671139118002110910800101000000000050200622131626704160000800102671226712267122671226712
80024267112000000000417006180000212802516001016001080010163142049236312671126711166233166858001080020800202671139118002110910800101000004703005020062216626704160000800102671226712267122671226712
80024267112000000000000618000021280251600101600108001016314214923631267112671116623316685800108002080020267113911800211091080010100000000015020062261326704160000800102671226712267122671226712
800242671120000000000006180000212802516001016001080010163142049236312671126711166233166858001080020800202671139118002110910800101004000000050200622161626704160000800102671226712267122671226712
80024267112000000000000618000021280251600101600108001016314204923631267112671116623316685800108002080020267113911800211091080010100000000005020062261626704160000800102671226712267122671226712
80024267112000000000000618000021280251600101600108001016314204923631267112671116623316685800108002080020267113911800211091080010100000000005020062216626704160000800102671226712267122671226712
800242671120000000000006180000212802516001016001080010163142049236312671126711166233166858001080020800202671139118002110910800101000000000050200162216626704160000800102671226712267122671226712
80024267111990000000000618000021280251600101600108001016314204923631267112671116623316685800108002080020267113911800211091080010100000003005020062261626704160000800102671226712267122671226712