Firestorm: MVN (register, lsr, 32-bit) measurements

Code:

  mvn w0, w0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	1	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	26	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	0	2035	2035	1575	3	1842	1000	1000	1000	2035	42	1	1	1001	1000	0	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  mvn w0, w0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	3	61	10000	19803	25	20100	20100	10111	184985	0	49	16955	20035	20035	18477	7	18736	10111	10232	10232	20035	42	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	19845	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10111	184985	1	49	16955	20035	20035	18477	7	18735	10111	10232	10232	20035	42	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	19845	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10111	184985	1	49	16955	20035	20035	18477	7	18735	10111	10232	10232	20035	42	1	1	10201	100	99	100	10100	100	0	0	1	1	1	720	0	16	0	0	19845	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10111	184985	0	49	16955	20035	20035	18477	7	18735	10111	10232	10232	20035	42	1	1	10201	100	99	100	10100	100	2	0	1	1	1	720	0	16	0	0	19845	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10111	184985	0	49	16955	20035	20035	18477	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	42	562	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	27	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	6	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	12	61	10000	19803	25	20100	20100	10100	185342	0	49	16955	20035	20035	18429	3	18700	10100	10200	10200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20081

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	0	0	213	0	0	82	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	4	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	3	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	3	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	4	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	81	0	0	82	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	4	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	18	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	3	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	3	63	4	3	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	75	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	4	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	9	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	3	63	3	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	267	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	4	4	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	49	16955	20035	20035	18451	3	18718	10010	10020	10020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	4	63	3	4	19792	20000	10010	20036	20036	20036	20036	20036

Test 3: throughput

Count: 8

Code:

  mvn w0, w8, lsr #17
  mvn w1, w8, lsr #17
  mvn w2, w8, lsr #17
  mvn w3, w8, lsr #17
  mvn w4, w8, lsr #17
  mvn w5, w8, lsr #17
  mvn w6, w8, lsr #17
  mvn w7, w8, lsr #17

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3344

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26768	200	0	0	0	0	0	0	33	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	414	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23652	26732	26731	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26732	26733	26733	26733	26733
80204	26732	201	0	0	0	0	0	0	15	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23651	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26728	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	3	0	0	49	80031	26146	28	160182	160182	80262	161906	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26732	26733
80204	26732	200	0	0	0	0	0	0	3	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23651	26732	26732	16651	7	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	15	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23652	26732	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26732	26733	26733
80204	26732	200	0	0	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23652	26731	26732	16651	8	16661	80262	80376	80376	26732	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733
80204	26732	200	0	0	0	0	0	0	0	0	0	28	80031	26146	28	160182	160182	80262	161906	0	49	23652	26732	26732	16651	8	16661	80262	80600	80376	26787	39	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5129	0	16	0	0	26729	160082	80100	26733	26733	26733	26733	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26734	200	0	0	0	0	0	0	0	30	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	17	22	16	16	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	16	22	7	16	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80416	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	6	22	13	16	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	417	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	47	0	3	0	0	5020	0	6	22	16	6	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	1	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	1	5020	0	6	22	6	13	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	4	0	0	0	0	0	0	0	5020	0	6	22	16	16	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	6	22	6	16	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	6	22	16	6	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	0	5020	0	16	22	16	6	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	199	0	0	0	0	0	0	0	0	0	0	61	80000	21280	25	160010	160010	80010	163142	0	49	23631	26711	26711	16623	3	16685	80010	80020	80020	26711	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	3	0	0	5020	0	6	22	6	16	26704	160000	80010	26712	26712	26712	26712	26712

MVN (register, lsr, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations