Firestorm: TBZ (taken) measurements

Code:

  tbz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3117	18	0	0	0	0	35	25	1000	1000	1000	5000	1	1956	1932	3	16	1000	1000	1000	2042	1952	1	1	1001	1000	1000	0	0	0	0	0	0	1818	638	968	518	479	2065	2085	1983	2001	2035	2007
1004	2002	15	0	0	0	0	35	25	1000	1000	1000	5000	1	1898	1990	3	18	1000	1000	1000	1882	1986	1	1	1001	1000	1000	0	0	0	0	0	0	1936	445	1048	465	522	1989	1997	2023	1863	2165	2011
1004	1976	15	0	0	0	0	35	25	1000	1000	1000	5000	1	2062	1966	3	18	1000	1000	1000	1864	2036	1	1	1001	1000	1000	0	0	0	0	0	0	1930	463	988	464	532	1963	2139	1989	1909	2059	2025
1004	1996	15	0	0	0	0	35	25	1000	1000	1000	5000	1	2058	2064	3	16	1000	1000	1000	1964	2094	1	1	1001	1000	1000	0	0	0	0	0	0	1952	502	944	512	443	1985	2075	1997	1865	2067	2023
1004	2010	15	0	0	0	0	35	25	1000	1000	1000	5000	1	2052	1994	3	18	1000	1000	1000	2054	1964	1	1	1001	1000	1000	0	0	0	0	0	0	1946	513	932	531	466	2069	1949	2011	2013	1845	1981
1004	1970	14	0	0	0	0	35	25	1000	1000	1000	5000	1	1970	1862	3	18	1000	1000	1000	1974	1986	1	1	1001	1000	1000	0	0	0	0	0	0	1924	477	968	499	467	1925	1951	2021	1985	1855	1987
1004	1948	15	0	0	0	0	35	25	1000	1000	1000	5000	1	1884	1962	3	18	1000	1000	1000	1962	1962	1	1	1001	1000	1000	0	0	0	0	0	0	1918	463	900	424	470	1929	2065	1965	2011	2013	2071
1004	1974	15	0	0	0	0	35	25	1000	1000	1000	5000	1	1946	2008	3	18	1000	1000	1000	1952	2020	1	1	1001	1000	1000	0	0	0	0	0	0	1922	452	1048	466	499	1877	1935	2007	2007	2035	2061
1004	1966	15	1	0	9	0	35	25	1000	1000	1000	5000	1	1970	2034	3	18	1000	1000	1000	2034	2010	1	1	1001	1000	1000	0	0	0	0	0	0	1920	426	942	475	510	2057	1945	2041	2061	1959	2051
1004	1972	16	0	0	0	0	35	25	1000	1000	1000	5000	1	1954	2036	3	18	1000	1000	1000	2158	1980	1	1	1001	1000	1000	0	0	0	0	0	0	1846	523	958	472	490	2055	1963	2013	1945	2027	1843

Count: 8

Code:

  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4
  tbz x0, #1, .+4

Initialization

  mov x0, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0095

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	81071	605	0	0	0	28	27	80105	80105	80107	400530	1	49	77684	80766	80766	6	10	80107	80207	80207	80774	64726	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80753	437	685	322	322	80769	100	80757	80765	80765	80775	80765
80204	80782	604	0	0	0	28	27	80105	80105	80107	400530	0	49	77686	80768	80768	6	10	80107	80207	80207	80766	64726	1	1	80201	80100	80099	100	100	100	0	18	0	1	1	1	80737	310	635	314	311	80759	100	80767	80769	80773	80783	80763
80204	80758	604	0	0	0	693	27	80105	80105	80107	400530	0	49	77702	80770	80780	6	10	80107	80207	80207	80792	64748	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80757	320	655	319	319	80767	100	80777	80777	80773	80779	80775
80204	80768	605	0	0	0	28	27	80105	80105	80107	400530	0	49	77676	80764	80764	6	10	80107	80207	80207	80764	64720	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80747	313	645	315	315	80767	100	80769	80767	80769	80759	80765
80204	80762	605	0	0	0	28	27	80105	80105	80107	400530	1	49	77678	80766	80768	6	10	80107	80207	80207	80756	64795	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80743	314	639	314	311	80761	100	80773	80765	80765	80767	80759
80204	80758	604	0	0	0	28	27	80105	80105	80107	400530	0	49	77684	80760	80764	6	10	80107	80207	80207	80772	64720	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80747	316	637	311	313	80851	100	80839	80771	80765	80773	80763
80204	80758	605	0	0	0	693	27	80105	80105	80107	400530	0	49	77694	80772	80768	6	10	80107	80207	80207	80772	64730	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80739	311	643	313	311	80757	100	80761	80763	80761	80771	80757
80204	80764	605	0	0	0	28	27	80105	80105	80107	400530	0	49	77688	80762	80768	6	10	80107	80207	80207	80760	64718	1	1	80201	80100	80099	100	100	100	1	0	0	1	1	1	80747	315	647	315	414	80761	100	80769	80765	80765	80755	80771
80204	80766	605	0	0	0	28	27	80105	80105	80107	400530	0	49	77692	80776	80778	6	10	80107	80207	80207	80790	64740	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80745	314	643	318	314	80767	100	80777	80777	80773	80773	80775
80204	80774	605	0	0	12	28	27	80105	80105	80107	400530	0	49	77686	80762	80760	6	10	80107	80207	80207	80766	64720	1	1	80201	80100	80099	100	100	100	0	0	0	1	1	1	80753	320	653	315	315	80759	100	80779	80763	80781	80771	80775

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80024	240149	1798	1	0	0	1	0	0	0	0	0	2	28	28	80011	80011	80012	400058	0	0	49	236964	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	1	0	1	1	1	240022	0	0	79836	160016	80002	80004	240041	10	240045	240048	240045	240045	240045
80024	240044	1798	1	0	0	1	0	0	0	0	0	2	28	28	80011	80011	80012	400058	0	0	49	236964	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240028	0	0	80005	160018	79999	80005	240047	10	240047	240047	240047	240045	240045
80024	240044	1798	1	0	0	1	0	0	0	0	0	2	28	28	80011	80011	80012	400058	0	0	49	236964	240044	240044	29	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240022	0	0	80003	160012	80002	80004	240041	10	240045	240081	240045	240041	240045
80024	240044	1798	1	0	0	1	0	0	0	0	0	2	714	28	80011	80011	80012	400058	0	0	49	236964	240044	240044	6	10	80069	80022	80022	240040	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240022	0	0	80003	160016	80002	80003	240041	10	240043	240045	240045	240045	240045
80024	240044	1798	1	0	0	1	0	0	0	0	0	2	693	28	80011	80011	80012	400058	1	0	49	236964	240044	240042	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240022	0	0	80003	160016	80002	80004	240039	10	240045	240045	240045	240045	240122
80024	240044	1798	1	0	0	1	0	0	0	0	0	2	693	28	80011	80011	80012	400058	1	0	49	236964	240044	240044	6	10	80012	80022	80056	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240022	0	0	80003	160016	80002	80004	240039	10	240045	240041	240045	240045	240045
80025	240044	1798	1	0	0	1	0	0	0	0	0	2	693	28	80011	80011	80012	400058	0	0	49	236964	240044	240044	6	10	80012	80022	80022	240065	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240030	0	0	80006	160024	80005	80007	240043	10	240049	240051	240045	240043	240045
80024	240044	1798	1	0	0	1	0	0	0	0	0	2	693	28	80011	80011	80012	400058	1	0	49	236964	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240022	0	0	80003	160016	80002	80004	240041	10	240045	240045	240045	240045	240045
80024	240044	1798	5	0	0	1	0	0	0	0	0	2	693	28	80011	80011	80012	400058	0	0	49	236964	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240022	0	0	80003	160016	80002	80004	240041	10	240045	240045	240045	240045	240045
80024	240044	1798	1	0	0	1	0	0	0	0	0	2	28	28	80011	80011	80012	400058	0	0	49	236964	240044	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	1	1	1	240022	0	0	80003	160016	80002	80003	240041	10	240047	240110	240106	240047	240111

TBZ (taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations