Firestorm: AND (register, lsl, 64-bit) measurements

Code:

  and x0, x0, x1, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	1	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	4	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	8	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1735	25	2000	2000	1000	32570	2035	2035	1575	3	1842	1000	1000	2000	2035	42	1	1	1001	1000	0	0	73	1	67	1	1	1781	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  and x0, x0, x1, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	2	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	24	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	6	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	726	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18717	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20080	150	0	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	189	0	82	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	3	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	36	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	61	10000	19803	25	20100	20100	10100	185342	1	3	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	3	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	9	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	4	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20069	20036	20036
10024	20035	150	0	0	12	0	61	10000	19771	25	20010	20010	10010	185310	0	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	1	3	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	9	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	249	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	20	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	543	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	258	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	3	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	82	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18455	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  and x0, x1, x0, lsl #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	84	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20069	20036	20036	20036	20036
10204	20035	150	0	0	6	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	1	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	9	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	24	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	6	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	429	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	9	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	1	3	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	6	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	61	10000	19803	25	20100	20100	10100	185342	1	49	16955	20035	20035	18429	3	18700	10100	10200	20200	20035	42	1	1	10201	100	99	100	10100	100	0	0	0	710	1	59	1	1	19791	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	0	54	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	0	0	0	9	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	1	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	441	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	13918	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	0	0	61	10000	19743	25	20010	20010	10010	185310	1	49	16955	20035	20035	18451	3	18718	10010	10020	20020	20035	42	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	0	0	640	2	63	2	2	19792	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  and x0, x8, x9, lsl #17
  and x1, x8, x9, lsl #17
  and x2, x8, x9, lsl #17
  and x3, x8, x9, lsl #17
  and x4, x8, x9, lsl #17
  and x5, x8, x9, lsl #17
  and x6, x8, x9, lsl #17
  and x7, x8, x9, lsl #17

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26748	200	0	0	61	80000	26094	25	160100	160100	80100	164318	1	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	1	6	0	5110	3	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	145	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	9	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	201	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	82	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	0	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726
80204	26725	200	0	0	61	80000	26094	25	160100	160100	80100	164318	0	49	23645	26725	26725	16615	0	3	16677	80100	80200	160200	26725	39	1	1	80201	100	99	100	80100	100	1	0	0	5110	2	22	2	2	26717	160000	80100	26726	26726	26726	26726	26726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26717	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	1	0	0	5020	0	0	5	22	0	5	3	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	1	0	0	5020	0	0	3	22	0	3	5	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	199	0	0	61	80000	21280	25	160010	160010	80010	163142	0	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	2	3	0	5020	0	0	5	22	0	3	5	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	1	0	0	5020	0	0	5	22	0	3	5	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	1	49	23631	26711	26711	16609	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	3	3	0	5020	0	0	5	22	0	3	5	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	45	0	0	5020	0	0	5	22	0	5	3	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	1	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	30	3	0	5020	0	0	5	22	0	5	5	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	1	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	1	6	0	5020	3	0	5	22	0	6	6	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	1	1	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	0	39	0	5020	0	0	5	22	0	3	5	26704	160000	80010	26712	26712	26712	26712	26712
80024	26711	200	0	0	61	80000	21280	25	160010	160010	80010	163142	0	0	49	23631	26711	26711	16623	0	3	16685	80010	80020	160020	26711	39	1	1	80021	10	9	10	80010	10	2	6	0	5020	0	0	5	22	0	5	4	26704	160000	80010	26712	26712	26712	26712	26712

AND (register, lsl, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations