Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AND (register, lsl, 64-bit)

Test 1: uops

Code:

  and x0, x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100010731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100040731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100080731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  and x0, x0, x1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000611000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103259111979120000101002003620036200362003620036
1020420035150240611000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
102042003515060611000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
1020420035150007261000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421349169552003520035184293187171010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
102042008015000611000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
10204200351501890821000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
102042003515030611000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
1020420035150360611000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036
102042003515000611000019803252010020100101001853421349169552003520035184293187001010010200202002003542111020110099100101001000007103159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000640263221979220000100102003620036200362003620036
10024200351500090611000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000000640263421979220000100102003620036200362003620036
10024200351490000611000019743252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000000640263221979220000100102003620036200692003620036
100242003515000120611000019771252001020010100101853100491695520035200351845131871810010100202002020035421110021109101001010000130640263221979220000100102003620036200362003620036
10024200351500090611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000640263221979220000100102003620036200362003620036
10024200351500024906110000197432520010200101001018531014916955200352003518451201871810010100202002020035421110021109101001010000000640263221979220000100102003620036200362003620036
1002420035150005430611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000640263221979220000100102003620036200362003620036
1002420035150002580611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000030640263221979220000100102003620036200362003620036
10024200351500000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000640263221979220000100102003620036200362003620036
10024200351500000821000019743252001020010100101853101491695520035200351845531871810010100202002020035421110021109101001010000000640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  and x0, x1, x0, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000846110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002006920036200362003620036
10204200351500066110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100010710159111979120000101002003620036200362003620036
10204200351500096110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
102042003515000246110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
10204200351500066110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
1020420035150004296110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
10204200351500096110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100013710159111979120000101002003620036200362003620036
10204200351500066110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036
10204200351500006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515000005400611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351490000900611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263121979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
100242003515000000004411000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491391820035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036
10024200351500000000611000019743252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  and x0, x8, x9, lsl #17
  and x1, x8, x9, lsl #17
  and x2, x8, x9, lsl #17
  and x3, x8, x9, lsl #17
  and x4, x8, x9, lsl #17
  and x5, x8, x9, lsl #17
  and x6, x8, x9, lsl #17
  and x7, x8, x9, lsl #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426748200006180000260942516010016010080100164318149236452672526725166150316677801008020016020026725391180201100991008010010016051103222226717160000801002672626726267262672626726
80204267252000014580000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725200096180000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725201006180000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725200008280000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010000051102222226717160000801002672626726267262672626726
8020426725200006180000260942516010016010080100164318049236452672526725166150316677801008020016020026725391180201100991008010010010051102222226717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)03091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0l1i cache miss demand (d3)d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426717200006180000212802516001016001080010163142004923631267112671116623031668580010800201600202671139118002110910800101010050200052205326704160000800102671226712267122671226712
8002426711200006180000212802516001016001080010163142004923631267112671116623031668580010800201600202671139118002110910800101010050200032203526704160000800102671226712267122671226712
8002426711199006180000212802516001016001080010163142004923631267112671116623031668580010800201600202671139118002110910800101023050200052203526704160000800102671226712267122671226712
8002426711200006180000212802516001016001080010163142004923631267112671116623031668580010800201600202671139118002110910800101010050200052203526704160000800102671226712267122671226712
8002426711200006180000212802516001016001080010163142014923631267112671116609031668580010800201600202671139118002110910800101033050200052203526704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631420049236312671126711166230316685800108002016002026711391180021109108001010450050200052205326704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631420149236312671126711166230316685800108002016002026711391180021109108001010303050200052205526704160000800102671226712267122671226712
8002426711200006180000212802516001016001080010163142014923631267112671116623031668580010800201600202671139118002110910800101016050203052206626704160000800102671226712267122671226712
80024267112000061800002128025160010160010800101631421149236312671126711166230316685800108002016002026711391180021109108001010039050200052203526704160000800102671226712267122671226712
8002426711200006180000212802516001016001080010163142004923631267112671116623031668580010800201600202671139118002110910800101026050200052205426704160000800102671226712267122671226712