Firestorm: MOV (from sp, 32-bit) measurements

Code:

  mov w0, wsp

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	202	1	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	3	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	2	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	1	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	1	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	1	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	2	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	1	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	2	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	69	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	1	0	56	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203
1004	202	2	0	35	25	1000	1000	1000	5000	202	202	39	3	57	1000	1000	1000	202	39	1	1	1001	1000	0	0	73	1	19	1	1	199	1000	1000	203	203	203	203	203

Count: 8

Code:

  mov w0, wsp
  mov w1, wsp
  mov w2, wsp
  mov w3, wsp
  mov w4, wsp
  mov w5, wsp
  mov w6, wsp
  mov w7, wsp

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13420	104	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	1	81	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	104	0	0	12	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	1	0	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	104	0	0	0	0	77	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	1	0	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	104	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	17	3	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	103	0	0	0	0	35	25	80100	80100	80100	410335	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	0	3	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	104	0	0	0	0	35	25	80100	80100	80100	400500	1	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80202	100	99	100	80100	100	0	37	0	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	104	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	33	3	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	103	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	0	3	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	104	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	80200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	103	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80263	80200	13386	39	1	1	80201	100	99	100	80100	100	0	1	0	0	5111	2	19	2	2	13383	80000	80100	13387	13387	13387	13387	13387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch indir mispred nonspec (c6)	cf	d2	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	13387	104	0	12	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	6	2	0	0	0	5029	0	0	15	19	25	15	13368	80000	0	80010	13392	13372	13372	13372	13372
80024	13371	104	0	0	35	25	80010	80010	80010	400713	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5029	0	0	14	19	26	15	13368	80000	0	80010	13392	13372	13372	13372	13372
80024	13371	103	0	12	105	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5	5031	0	0	29	19	27	27	13368	80000	0	80010	13375	13372	13372	13372	13372
80024	13371	104	0	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5029	0	0	12	19	27	14	13368	80000	0	80010	13375	13372	13372	13372	13372
80024	13371	104	0	9	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5031	0	0	25	19	15	26	13368	80000	0	80010	13421	13372	13372	13372	13372
80024	13371	104	0	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	7	0	0	0	0	5027	0	0	14	19	27	28	13368	80000	0	80010	13391	13372	13372	13372	13372
80024	13371	103	0	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	3	0	0	5032	0	0	27	19	19	27	13368	80000	0	80010	13402	13372	13372	13372	13372
80024	13371	103	0	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	3	0	0	5031	0	0	24	19	19	26	13368	80000	0	80010	13392	13372	13372	13372	13372
80024	13371	103	0	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	2	1	80021	10	9	10	80010	10	0	0	0	3	0	0	5027	0	0	13	19	27	15	13368	80000	0	80010	13391	13372	13372	13372	13372
80024	13371	103	0	0	35	25	80010	80010	80010	400050	0	49	10291	13371	13371	3330	3	3348	80010	80020	80020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5031	0	0	27	19	26	26	13368	80000	0	80010	13391	13372	13372	13372	13372

MOV (from sp, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations