Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UBFIZ (32-bit)

Test 1: uops

Code:

  ubfiz w0, w0, #3, #7
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035812618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
10041035718618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  ubfiz w0, w0, #3, #7
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102041003575606198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750014798772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035750053698772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
1020410035751506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575606198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575906198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575006198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575008298772510100101001010088664496955100351003586063872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)0318191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100357500061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036
10024100357501061986325100101001010010887841496955100351007286023874010010100201002010035411110021109101001010064024122994010000100101003610036100771003610036
10024100357500061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036
10024100357500061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036
10024100357500061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036
1002410035760030061986325100101001010010887841496955100351003586023874010010100201002010035412110021109101001010064024122994010000100101003610036100361003610036
100241003575000893986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036
1002410035750001025986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036
10024100357500061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036
10024100357500061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010064024122994010000100101003610036100361003610036

Test 3: throughput

Count: 8

Code:

  ubfiz w0, w8, #3, #7
  ubfiz w1, w8, #3, #7
  ubfiz w2, w8, #3, #7
  ubfiz w3, w8, #3, #7
  ubfiz w4, w8, #3, #7
  ubfiz w5, w8, #3, #7
  ubfiz w6, w8, #3, #7
  ubfiz w7, w8, #3, #7
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413415100101000300282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001339113391133911339113391
8020413390100101000000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001339113391133911339113391
8020413390100101000000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001339113391133911339113391
80204133901001010001800282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001339113391133911339113391
80204133901001010002700282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001339113391133911339113391
8020413390101101000000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001339113391133911339113391
8020413390100101000000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001339113391133911339113391
8020413390100101000000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000001115119116111338780036801001351713576133911339113391
8020413390100101000000282780136801368014840071014910310133901339033266333680148802648026413390391180201100991008010010000000001115177195111356880553801001359613580136241357713641
802041357710010114339926402571258013680527806764026540491049813575136483327213390804118066880795135863941802011009910080100100000102138822251872111221355080415801001359113591136511358913635

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)191e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002413377100000352580010800108001040005020491029113371133713330333488001080020800201337139118002110910800101005021519561336880000800101337213372133721337213372
800241337110000132352580010800108001040005020491029113371133713330333488001080020800201337139118002110910800101005021619561336880000800101337213372133721337213372
8002413371100100352580010800108001040005040491029113371133713330333488001080020800201337139118002110910800101005021519661336880000800101337213372133721337213372
8002413371100000352580010800108001040005051491029113371133713330333488001080020800201337139118002110910800101005021519551336880000800101337213372133721337213372
8002413371100000352580010800108001040005040491029113371133713330333488001080020800201337139118002110910800101005021519551336880000800101337213372133721337213372
8002413371100003352580010800108001040005040491029113371133713330333488001080020800201337139118002110910800101005022619651336880000800101337213372133721337213372
8002413371100000352580010800108001040005040491029113371133713330333488001080020800201337139118002110910800101005021519651336880000800101337213372133721337213372
8002413371100000352580010800108001040005050491029113371133713330333488001080020800201337139118002110910800101005021619651336880000800101337213372133721337213372
80024133711000012352580010800108001040005040491029113371133713330333488001080020800201337139118002110910800101005022519541336880000800101337213372133721337213372
8002413371100000352580010800108001040005040491029113371133713330333488001080020800201337139118002110910800101005021619751336880000800101337213372133721337213372