Firestorm: STP (32-bit) measurements

Code:

  stp w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	563	4	1	1	1	1	0	18	1	0	1	539	16	16	1	25	1000	1000	1000	23508	0	554	552	367	3	412	1000	1000	3000	554	552	1	1	1001	1000	1000	1015	16	44	0	0	1016	0	2	18	1002	16	42	14	2	73	2	16	1	1	550	1000	555	555	553	553	553
1004	564	4	1	0	1	1	0	17	1	0	1	539	16	16	2	25	1000	1000	1000	23004	0	551	554	366	3	412	1000	1000	3000	553	554	1	1	1001	1000	1000	1014	15	44	0	1	1016	0	0	18	1002	16	44	14	1	73	1	16	1	1	551	1000	555	555	555	555	555
1004	553	4	1	1	1	1	0	20	1	0	1	538	16	16	2	25	1000	1000	1000	23028	0	554	563	367	3	421	1000	1000	3000	554	551	1	1	1001	1000	1000	1016	14	44	1	1	1016	0	1	17	1002	16	44	14	1	73	1	16	1	1	551	1000	555	555	555	555	554
1004	552	4	1	1	0	0	0	17	1	0	1	539	16	16	6	25	1000	1000	1000	22956	0	563	554	365	3	412	1000	1000	3000	552	554	1	1	1001	1000	1000	1014	14	44	0	2	1016	0	2	18	1002	16	44	14	1	73	1	16	1	1	551	1000	555	553	553	564	564
1004	554	4	1	1	0	1	0	17	1	0	1	539	16	16	6	25	1000	1000	1000	23438	0	554	552	367	3	409	1000	1000	3000	554	554	1	1	1001	1000	1000	1014	14	44	0	0	1016	1	0	16	1002	16	44	14	2	73	1	16	1	1	551	1000	555	555	555	554	553
1004	552	4	1	0	0	1	0	21	1	0	1	539	16	16	4	25	1000	1000	1000	22908	0	554	553	367	3	410	1000	1000	3000	554	554	1	1	1001	1000	1000	1014	14	44	0	0	1016	0	0	19	1002	16	44	14	1	73	1	16	1	1	549	1000	555	555	555	554	553
1004	551	4	1	1	1	1	0	20	1	0	1	539	16	16	1	25	1000	1000	1000	23028	0	554	552	367	3	410	1000	1000	3000	554	553	1	1	1001	1000	1000	1016	14	44	0	0	1016	0	2	16	1002	16	43	14	1	73	1	16	1	1	551	1000	553	553	565	555	555
1004	554	4	1	1	1	0	0	19	1	0	1	537	16	16	1	25	1000	1000	1000	23004	0	554	563	367	3	412	1000	1000	3000	554	552	1	1	1001	1000	1000	1016	15	44	0	1	1016	0	2	16	1002	16	44	14	0	73	1	16	1	1	551	1000	555	555	555	555	555
1004	553	4	1	1	1	1	0	17	1	0	1	539	16	16	1	25	1000	1000	1000	23004	0	552	554	364	3	412	1000	1000	3000	551	554	1	1	1001	1000	1000	1014	15	44	0	1	1016	0	1	18	1002	16	44	14	2	73	1	16	1	1	551	1000	555	555	555	553	553
1004	552	4	1	1	1	1	0	17	1	0	1	537	15	16	1	25	1000	1000	1000	23004	1	554	553	376	3	410	1000	1000	3000	563	554	1	1	1001	1000	1000	1015	15	44	0	1	1016	0	0	17	1002	16	42	14	0	73	1	16	1	1	549	1000	552	553	564	556	555

Count: 8

Code:

  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]
  stp w0, w1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	299	0	0	0	12	9	0	0	40025	0	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36971	40042	40042	29955	3	30000	80100	200	80000	200	240000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80000	0	0	80002	2	34	0	0	5110	0	1	16	1	1	40037	80000	100	40052	40043	40052	40043	40041
80204	40040	300	0	0	0	0	0	1	0	40027	16	0	0	25	80100	100	80000	102	80000	500	1839424	0	49	36960	40042	40042	29953	3	30000	80100	200	80000	200	240000	40042	32004	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	80002	2	34	0	0	5110	0	1	16	1	1	40039	80000	100	40041	40052	40043	40051	40043
80204	40040	300	0	0	0	0	9	0	0	40035	0	0	0	25	80100	100	80000	100	80000	500	1839352	1	49	36962	40049	40042	29955	3	30000	80100	200	80000	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	8	80000	2	0	0	0	5110	0	1	16	1	1	40039	80000	100	40043	40050	40043	40043	40043
80204	40040	300	0	0	0	0	0	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36962	40042	40042	29953	3	30007	80100	202	80121	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	2	80000	0	0	0	0	5110	0	1	16	1	1	40037	80000	100	40041	40043	40041	40041	40043
80204	40040	300	0	0	0	0	3	1	0	40036	0	16	0	25	80100	100	80000	100	80000	500	1839352	1	49	36970	40042	40042	29955	3	30007	80100	200	80000	200	240000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80000	0	5	80002	2	34	0	0	5110	0	1	16	1	1	40039	80000	100	40043	40043	40041	40043	40041
80204	40042	300	0	0	0	0	0	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839424	1	49	36962	40042	40042	29953	3	30007	80100	200	80000	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	1	2	80002	2	0	0	0	5110	0	1	16	1	1	40037	80000	100	40041	40043	40041	40043	40052
80204	40042	300	1	0	0	0	6	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839860	0	49	36962	40042	40040	29955	3	30000	80100	200	80000	200	240000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	0	80002	2	34	0	0	5110	1	1	16	1	1	40039	80000	100	40043	40050	40041	40051	40043
80204	40042	300	0	0	0	0	9	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839352	0	49	36969	40042	40042	29953	3	30008	80100	200	80000	200	240000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	80000	2	0	0	0	5110	0	1	16	1	1	40039	80000	100	40051	40043	40041	40041	40043
80204	40042	300	0	0	0	0	3	0	1	40025	16	0	0	25	80100	100	80000	100	80000	500	1839352	0	49	36960	40042	40042	29955	3	30009	80100	200	80000	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	0	80002	0	0	80002	2	34	0	0	5110	0	1	16	1	1	40039	80000	100	40043	40043	40043	40050	40041
80204	40042	300	0	0	0	0	3	0	0	40025	0	16	0	25	80100	100	80000	100	80000	500	1839692	0	49	36962	40051	40042	29963	3	30000	80100	200	80000	200	240000	40051	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	28	80002	0	0	80002	0	34	0	0	5110	0	1	16	1	1	40037	80000	100	40041	40041	40051	40043	40052

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40054	300	1	1	1	0	17	1	0	0	1	40039	16	16	5	25	80010	10	80000	10	80000	50	1839884	1	49	36973	40063	40051	29987	3	30032	80010	20	80000	20	240000	40054	40063	1	1	80021	10	9	10	80000	10	80000	10	80016	15	44	0	1	80016	0	0	16	80002	16	44	14	1	0	5020	7	16	2	2	40051	80000	10	40054	40055	40055	40048	40052
80024	40054	300	1	1	0	0	19	1	0	0	1	40039	16	0	2	25	80010	10	80000	10	80000	50	1840004	0	49	36974	40052	40052	29982	3	30034	80010	20	80000	20	240000	40052	40053	1	1	80021	10	9	10	80000	10	80000	10	80014	16	44	0	1	80016	0	1	30	80002	16	44	14	1	0	5020	3	16	2	6	40051	80000	10	40054	40055	40055	40065	40053
80024	40054	300	1	1	1	0	15	1	0	0	1	40039	16	16	7	25	80010	10	80000	10	80000	50	1840028	0	49	36974	40052	40052	29987	3	30034	80010	20	80000	20	240000	40052	40053	1	1	80021	10	9	10	80000	10	80000	10	80015	14	44	0	0	80016	0	0	35	80002	16	44	14	2	0	5020	2	16	2	6	40049	80000	10	40053	40048	40048	40048	40065
80024	40054	300	1	1	1	6	18	1	0	0	1	40038	0	16	5	25	80010	10	80000	10	80000	50	1840028	0	49	36972	40054	40063	29999	3	30032	80010	20	80000	20	240000	40054	40052	1	1	80021	10	9	10	80000	10	80000	10	80016	14	44	0	1	80016	0	0	51	80240	14	44	14	0	0	5020	2	16	2	2	40051	80000	10	40055	40053	40055	40053	40055
80024	40057	300	1	0	0	0	17	1	0	0	1	40039	16	16	0	25	80010	10	80000	10	80000	50	1839956	0	49	36975	40054	40047	29989	3	30043	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80015	14	44	0	0	80014	0	1	18	80002	14	44	14	0	0	5020	2	16	6	2	40049	80000	10	40065	40055	40064	40055	40055
80024	40047	299	1	0	0	0	20	1	0	0	1	40039	16	16	5	25	80010	10	80000	10	80000	50	1840028	1	49	36974	40054	40054	29989	3	30027	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	15	44	0	0	80014	1	1	17	80000	14	0	14	0	0	5020	2	16	2	2	40049	80000	10	40064	40055	40064	40055	40055
80024	40052	300	1	1	1	9	17	1	0	0	1	40037	16	16	6	25	80010	10	80000	10	80000	50	1840028	0	49	36974	40052	40052	29987	3	30034	80010	20	80000	20	240000	40052	40053	1	1	80021	10	9	10	80000	10	80000	10	80014	14	44	0	0	80016	0	1	26	80002	16	44	14	1	0	5020	2	16	2	2	40061	80000	10	40055	40053	40056	40054	40055
80024	40052	300	1	1	0	0	14	0	0	0	1	40039	15	16	1	25	80010	10	80000	10	80000	50	1839908	0	49	36974	40054	40054	29989	3	30028	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	15	44	0	1	80016	0	0	22	80002	16	44	14	1	0	5020	2	16	2	2	40045	80000	10	40056	40054	40048	40055	40055
80024	40047	300	1	1	1	0	19	0	0	0	1	40036	16	16	6	25	80010	10	80000	10	80000	50	1840439	0	49	36967	40053	40054	29989	3	30032	80010	20	80000	20	240000	40054	40052	1	1	80021	10	9	10	80000	10	80000	10	80015	15	44	0	1	80016	0	0	48	80242	16	44	14	0	0	5020	2	16	6	2	40049	80000	10	40055	40053	40055	40053	40055
80024	40054	300	1	1	1	0	22	1	0	0	1	40039	16	16	0	25	80010	10	80000	10	80000	50	1840486	0	49	36974	40053	40054	29989	3	30027	80010	20	80000	20	240000	40047	40054	1	1	80021	10	9	10	80000	10	80000	10	80015	15	44	0	1	80016	0	1	17	80002	16	44	14	0	0	5020	2	16	2	2	40052	80000	10	40048	40053	40055	40048	40048

STP (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations