Firestorm: SBCS (64-bit) measurements

Code:

  sbcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	2	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	0	0	0	24	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	0	95	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	6	0	0	0	0	73	2	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	3	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	0	0	0	0	0	0	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	0	0	0	73	3	27	3	3	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  sbcs x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	1	18	569	9920	25	10100	10100	10100	647152	1	49	6955	10035	10082	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	9	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10084
10204	10035	75	1	0	362	9920	25	10100	10100	10100	647152	1	49	6955	10097	10082	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	3	735	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	1	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	91	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	1	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	2	27	2	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	6	0	640	3	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	4	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	15	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	9	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	93	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	102	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	13	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	20	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  sbcs x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	282	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	476	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	2	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	1	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	82	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	9	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10106	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 1->4

Chain cycles: 1

Code:

  sbcs x0, x1, x2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	61	19930	25	20200	20200	20212	1297733	49	16955	20035	20035	17425	7	17486	20212	20224	40248	20035	64	1	1	20201	100	99	20100	0	0	0	1	1	1	1319	2	16	1	1	20015	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	61	19930	25	20200	20200	20212	1297733	49	16955	20035	20035	17425	7	17486	20212	20224	40248	20035	64	1	1	20201	100	99	20100	0	0	0	1	1	1	1319	1	16	1	1	20015	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	841	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	4	3	0	0	0	1310	2	28	2	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	1	0	0	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	156	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	126	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	29	6	0	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	43	177	0	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	422	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	145	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	61	19926	25	20200	20200	20200	1297650	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	1310	2	28	2	2	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	1	1	19995	20032	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19917	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	2	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	36	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	120	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	283	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	3	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	102	0	1270	1	27	1	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	0	49	16955	0	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	66	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036

Test 5: Latency 4->2

Chain cycles: 1

Code:

  sbcs x0, x1, x2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	15	147	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	166	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	0	726	19930	45	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	124	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	444	84	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	103	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	5	0	1	1	1	1320	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	1	1	1	1319	16	20012	20000	20100	20036	20082	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	170	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	1	0	0	1270	3	27	4	6	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	4	7	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	170	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	3	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	105	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	3	78	0	1270	4	27	4	7	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	4	7	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	4	7	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	145	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	5	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	105	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	5	27	5	7	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	4	8	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	145	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	1270	4	27	5	8	19995	20000	20010	20036	20036	20036	20036	20036

Test 6: Latency 4->3

Chain cycles: 1

Code:

  sbcs x0, x1, x2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	100	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	1	0	3	1	1	1	1320	16	0	1	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40438	20035	64	2	1	20201	100	99	100	20100	10100	0	0	0	12	1	1	1	1319	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036
20205	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	249	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1319	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	254	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	16	0	0	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	496	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	1	1	1	1320	16	1	0	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	149	0	0	0	0	0	103	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	7	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	1	0	0	1270	2	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	82	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	84	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	3	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	6	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	84	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	21	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	126	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	1	0	0	0	0	103	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	162	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036

Test 7: Latency 4->4

Code:

  sbcs x0, x1, x2

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	251	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8736	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	520	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	2	3	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	1	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	344	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	1123	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8736	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	2	2	0	0	1	1	1	720	16	10013	10100	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	632	9918	25	10020	10020	10020	647296	49	6956	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	640	2	27	4	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	640	3	27	4	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	1	3	640	2	27	4	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30308	10035	40	1	1	10021	10	9	10010	0	0	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	640	3	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6956	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	3	640	4	27	4	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	9	640	2	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	0	640	3	27	3	3	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	103	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	30416	10035	40	1	1	10021	10	9	10010	0	0	0	0	640	3	27	2	3	9997	10010	10010	10036	10036	10036	10036	10036

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  sbcs x0, x8, x9
  ands xzr, xzr, xzr
  sbcs x1, x8, x9
  ands xzr, xzr, xzr
  sbcs x2, x8, x9
  ands xzr, xzr, xzr
  sbcs x3, x8, x9
  ands xzr, xzr, xzr
  sbcs x4, x8, x9
  ands xzr, xzr, xzr
  sbcs x5, x8, x9
  ands xzr, xzr, xzr
  sbcs x6, x8, x9
  ands xzr, xzr, xzr
  sbcs x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53408	399	1	0	1	0	0	1	0	0	1	706	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	6	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10114	10	19	13	14	53401	160000	80100	53405	53405	53405	53405	53405
160204	53452	400	1	0	1	0	0	0	0	0	1	41	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10112	12	19	12	12	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	1	0	0	0	0	0	1	41	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10112	12	19	11	8	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	399	1	0	1	0	0	0	39	0	1	41	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10112	8	19	11	8	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	1	0	0	0	0	0	1	41	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	4	6	0	10112	12	19	12	13	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	1	0	0	0	0	0	1	706	25	160100	160100	160100	1063588	0	49	50372	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10112	13	19	13	13	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	1	0	0	0	0	0	1	41	25	160235	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10114	14	19	15	13	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	1	0	0	0	165	0	2	41	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10114	15	19	13	11	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	1	0	0	0	0	0	1	169	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10112	7	19	7	10	53401	160000	80100	53405	53405	53405	53405	53405
160204	53452	400	1	0	1	0	0	0	720	0	1	83	25	160100	160100	160100	1063588	1	49	50324	53453	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	1	10112	7	19	12	13	53401	160000	80100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53380	399	1	0	1	0	0	0	0	0	1	46	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10024	8	1	1	24	19	2	38	1	17	20	53371	160000	15	9	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	1	0	0	0	0	0	1	46	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10024	8	1	1	19	19	2	32	1	16	18	53371	160000	15	9	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	1	0	0	0	0	0	1	74	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10024	8	1	1	14	19	2	31	2	17	18	53371	160000	30	17	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	1	0	0	0	0	0	1	46	25	160010	160010	160010	1029388	1	1	5	49	47259	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10028	8	1	1	21	19	4	31	1	16	18	53371	160000	15	17	80010	53375	53375	53375	53375	53375
160024	53374	399	1	0	1	0	0	0	0	0	1	46	25	160010	160010	160010	1029388	1	1	0	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10024	8	1	1	16	19	2	33	1	14	17	53371	160000	15	9	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	1	0	0	0	0	0	1	46	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10028	8	1	1	17	19	2	34	1	18	16	53371	160000	15	9	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	1	0	0	0	0	0	1	46	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10024	11	1	1	16	19	2	31	1	14	15	53371	160000	30	9	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	1	0	0	0	0	0	1	711	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10028	11	1	1	18	19	2	30	1	11	22	53371	160000	15	9	80010	53375	53375	53375	53375	53375
160024	53374	400	1	0	1	0	0	0	0	0	1	46	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10026	8	1	1	18	19	2	33	1	17	12	53371	160000	15	9	80010	53375	53375	53375	53375	53375
160024	53374	399	1	0	1	0	0	0	0	0	1	432	25	160010	160010	160010	1029388	1	1	5	49	50294	53374	53374	33324	3	33344	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	0	0	0	0	0	10026	11	2	1	12	17	2	29	1	21	19	53371	160000	30	9	80010	53375	53375	53375	53375	53375

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  sbcs x0, x4, x5
  sbcs x1, x4, x5
  sbcs x2, x4, x5
  sbcs x3, x4, x5

Initialization

  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13433	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	13383	13412	13412	6026	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	13	3	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	13383	13412	13412	5553	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	24	45	0	25	50100	40100	10000	40100	10000	574746	80000	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	13383	13412	13412	5553	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	12	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	13383	13412	13412	6026	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	13383	13412	13412	5553	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	13383	13412	13412	5553	3353	8	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	15	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	927	0	25	50100	40100	10000	40100	10000	586432	80000	13383	13412	13412	6026	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	15	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13383	100	0	0	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3142	8	19	9	7	13379	40072	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	10	19	9	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	8	19	9	7	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	48	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	9	19	8	7	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	88	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	8	19	7	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	57	0	3140	7	19	7	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	101	0	0	1	0	0	0	0	87	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	8	29	10	9	13379	40000	40010	13383	13383	13383	13383	13428
50024	13382	100	0	0	0	0	0	0	0	51	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	8	19	10	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	3	0	0	0	45	25	50010	40010	10000	40208	10000	573456	80000	1	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	7	19	8	8	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	0	0	0	0	0	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	0	0	0	3140	7	19	10	9	13379	40000	40010	13383	13383	13383	13383	13383

SBCS (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 4->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 9: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations