Firestorm: PACDA measurements

Code:

  pacda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	67	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	9	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	64	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2082	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	4	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	1	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	1	1	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  pacda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	607	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	0	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	0	20280	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70069	70030	70072	70030
10204	70029	614	0	0	0	0	0	0	0	0	726	59824	25	10200	10200	0	10200	1808703	1	49	66949	70029	70029	68480	3	68884	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	2	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	608	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	0	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	2	1	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	608	0	0	0	0	0	0	0	0	132	59824	25	10200	10200	0	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	0	710	2	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	609	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	0	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	615	0	0	0	0	0	12	0	0	61	59824	25	10200	10200	0	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10103	10100	70030	70030	70030	70030	70030
10204	70029	608	0	0	0	0	0	0	0	0	61	59819	25	10200	10200	0	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	609	0	0	0	0	0	0	0	0	104	59824	25	10200	10200	0	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	1	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	606	0	0	0	0	0	6	0	0	103	59824	25	10200	10200	0	10200	1808330	0	49	66949	70029	70069	68480	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	0	710	1	79	2	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70069	607	0	0	1	0	0	0	0	0	103	59824	25	10200	10200	0	10200	1808330	0	49	66949	70029	70029	68502	3	68674	10200	10200	0	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	3	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	621	0	103	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70068	68526	3	68722	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	9	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	633	9	107	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	651	21	249	59824	25	10023	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	651	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	1	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	650	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	0	640	4	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	96	59824	32	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	103	59824	25	10022	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	0	0	0	640	0	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  pacda x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	693	0	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20211	4943049	49	76949	80029	80029	76020	6	76228	20211	20227	40254	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	1	1	1	1920	1	16	1	1	79870	20100	30100	80030	80030	80030	80030	80030
30204	80029	793	1	0	0	0	0	0	0	0	0	726	69799	25	20200	20200	20211	4943049	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	694	0	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	693	0	0	0	0	0	0	0	0	0	89	69799	25	20200	20200	20200	4942601	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	20530	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	693	0	0	0	0	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	693	0	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	693	0	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	1	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	695	0	0	0	0	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	49	76949	80029	80073	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	693	0	0	0	0	0	0	0	12	0	103	69799	25	20200	20200	20200	4942994	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	34000	0	0	0	0	2305	2	274	2	1	80502	20208	30100	80930	80411	80030	80030	80030
30204	80029	694	0	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	80029	698	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	33	0	3	0	0	0	1890	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	705	0	0	0	0	0	12	0	0	61	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40238	80029	144	1	1	30021	10	9	30010	0	0	0	0	3	0	0	0	1890	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	697	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	2	0	0	0	0	0	1890	2	72	3	2	79803	20010	30010	80030	80030	80030	80030	80165
30024	80029	702	0	0	0	0	0	12	0	0	103	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30022	10	9	30010	0	0	2	0	9	0	0	0	1890	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	12	0	0	61	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	1	0	0	0	0	0	1890	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	704	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	3	0	0	0	0	0	1890	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	696	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	6	0	0	0	0	0	1890	2	31	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	701	0	0	0	0	0	0	0	0	117	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	4	0	0	0	0	0	1890	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80207
30024	80029	736	0	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	27	76233	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	1	0	0	0	0	0	1890	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	0	816	69799	25	20020	20020	20020	4952048	0	49	76949	0	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	4	0	0	0	0	0	1890	2	72	2	3	79803	20010	30010	80030	80030	80030	80030	80030

Test 4: throughput

Count: 8

Code:

  pacda x0, x8
  pacda x1, x8
  pacda x2, x8
  pacda x3, x8
  pacda x4, x8
  pacda x5, x8
  pacda x6, x8
  pacda x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5e	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9d	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	642	0	0	0	12	0	667	28	80205	80205	80207	401030	0	1	49	76960	80041	80040	69980	8	69990	80207	80224	160248	80040	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	1	1	1	5119	0	0	16	0	0	80038	80105	80100	80042	80042	80042	80042	80041
80204	80040	645	0	0	0	0	0	70	29	80205	80205	80207	401030	0	1	49	76961	80041	80041	69980	7	69990	80207	80224	160248	80041	164	1	1	80201	100	99	80100	0	0	0	0	0	3	0	1	1	1	5119	0	0	16	0	0	80038	80105	80100	80042	80042	80041	80041	80041
80204	80040	644	0	0	0	12	0	77	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	701	0	0	0	0	0	77	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	3	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	35	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	697	0	0	0	0	0	63	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	12	0	77	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	35	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	35	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	77	25	80200	80200	80200	401000	0	1	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	3	0	0	0	0	5110	0	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	699	0	0	0	0	0	0	0	811	25	80041	80020	80020	400100	1	49	76955	80035	80035	69988	3	70040	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	3	0	5020	0	0	0	5	25	0	0	3	4	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	12	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	5020	0	0	0	4	25	0	0	4	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	240	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80042	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5033	0	0	0	4	25	0	0	7	6	80024	80010	0	80010	80036	80082	80036	80036	80036
80024	80035	698	0	0	0	0	0	0	0	259	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	5020	0	0	0	4	25	1	1	8	3	80024	80010	15	80010	80036	80036	80036	80036	80036
80024	80035	698	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	2	12	0	5032	0	0	0	6	25	0	0	4	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	750	0	0	0	0	0	0	0	700	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	2	0	6	0	5020	0	0	0	4	25	0	0	4	5	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	698	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5020	0	0	0	4	25	0	0	4	4	80024	80010	0	80010	80073	80036	80036	80036	80036
80024	80081	698	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	1	0	0	0	5020	0	0	0	4	25	0	0	7	4	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	698	0	0	0	0	132	0	0	35	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	5020	0	0	0	7	25	0	0	4	4	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	0	700	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	160020	80035	164	11	1	80021	10	9	80010	0	4	0	1	2	12178	4	5335	0	0	1	6	217	0	0	10	5	80772	80493	0	80010	80036	80036	80036	80036	80036

PACDA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations