Firestorm: PRFM (register, PLIL3KEEP) measurements

Code:

  prfm plil3keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1627	12	33	16	32	2449	1574	890	25	1000	1000	1000	69632	1	1563	1579	1303	3	1477	1000	1000	1000	1577	1601	1	1	1001	259	2268	2270	3290	0	2476	2276	1000	73	1	16	1	1	1489	1000	1622	1624	1611	1588	1588
1004	1587	12	35	18	34	2461	1580	850	25	1000	1000	1000	68617	1	1574	1614	1317	3	1502	1000	1000	1000	1605	1585	1	1	1001	260	2248	2260	3270	0	2412	2267	1000	73	1	16	1	1	1499	1000	1609	1604	1565	1612	1581
1004	1626	12	33	18	36	2465	1598	898	25	1000	1000	1000	69230	1	1599	1612	1307	3	1401	1000	1000	1000	1572	1576	1	1	1001	257	2290	2291	3284	0	2451	2283	1000	73	1	16	1	1	1489	1000	1593	1623	1613	1614	1597
1004	1605	12	34	18	35	2418	1592	928	25	1000	1000	1000	68903	1	1594	1643	1326	3	1412	1000	1000	1000	1577	1545	1	1	1001	238	2308	2289	3277	0	2437	2257	1000	73	1	16	1	1	1500	1000	1607	1607	1619	1605	1627
1004	1623	12	35	15	33	2472	1619	903	25	1000	1000	1000	69177	1	1593	1582	1277	3	1433	1000	1000	1000	1595	1558	1	1	1001	241	2270	2250	3276	0	2447	2281	1000	73	1	16	1	1	1498	1000	1608	1629	1576	1597	1595
1004	1619	12	35	17	36	2439	1558	856	25	1000	1000	1000	70104	1	1597	1608	1296	3	1487	1000	1000	1000	1611	1617	1	1	1001	249	2293	2286	3275	0	2477	2250	1000	73	1	16	1	1	1499	1000	1585	1597	1616	1591	1605
1004	1620	12	34	16	35	2454	1621	881	25	1000	1000	1000	69353	1	1585	1619	1305	3	1457	1000	1000	1000	1600	1558	1	1	1001	261	2289	2296	3281	0	2468	2264	1000	73	1	16	1	1	1456	1000	1589	1594	1635	1583	1590
1004	1554	12	36	17	34	2447	1581	859	25	1000	1000	1000	68682	1	1605	1616	1278	3	1453	1000	1000	1000	1606	1591	1	1	1001	241	2279	2250	3270	0	2441	2256	1000	73	1	16	1	1	1517	1000	1613	1588	1586	1586	1616
1004	1593	12	33	18	33	2488	1583	915	25	1000	1000	1000	69972	1	1600	1621	1284	3	1493	1000	1000	1000	1595	1596	1	1	1001	235	2281	2286	3260	0	2460	2282	1000	73	1	16	1	1	1472	1000	1605	1620	1586	1588	1604
1004	1586	11	34	17	34	2473	1589	877	25	1000	1000	1000	68819	1	1554	1616	1285	3	1437	1000	1000	1000	1599	1597	1	1	1001	234	2276	2272	3279	0	2452	2247	1000	73	1	16	1	1	1522	1000	1622	1613	1599	1581	1584

Test 2: throughput

Code:

  prfm plil3keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5512

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15406	117	381	198	385	25072	0	15477	9528	25	20226	10214	10000	10100	10000	129006	722173	1	48	49	12448	15571	15462	12852	3	12958	20100	10200	10000	10200	10000	15547	149	1	1	20201	100	99	2056	100	10100	100	23161	23267	33266	0	24878	23380	10000	0	1310	2	16	2	2	15454	10132	10000	10100	15660	15658	15459	15594	15453
20204	15475	117	380	202	384	25048	0	15730	9731	46	20199	10324	10000	10100	10000	129466	725117	1	31	49	12610	15604	15608	12838	3	13237	20345	10323	10000	10326	10112	15530	152	1	1	20201	100	99	2093	100	10100	100	23451	23354	33458	0	25152	23344	10000	0	1310	2	16	2	2	15393	10111	10000	10100	15419	15528	15529	15493	15552
20204	15484	115	384	196	385	25155	0	15518	9645	25	20163	10205	10000	10100	10000	130441	726014	1	37	49	12386	15345	15483	12695	3	13006	20100	10200	10000	10200	10000	15443	149	1	1	20201	100	99	2019	100	10100	100	23182	23471	33338	0	25103	23246	10000	0	1310	2	16	2	2	15434	10132	10000	10100	15439	15444	15451	15557	15634
20204	15580	117	384	203	389	25050	0	15414	9551	25	20190	10202	10000	10100	10000	130103	731144	1	42	49	12385	15493	15436	12844	3	13094	20100	10200	10000	10200	10000	15453	154	1	1	20201	100	99	2115	100	10100	100	23125	23256	33328	0	24937	23546	10000	0	1311	2	16	2	2	15419	10120	10000	10100	15492	15511	15386	15348	15554
20204	15509	117	385	201	379	24996	0	15376	9584	25	20208	10205	10000	10100	10000	127978	718158	1	30	49	12485	15551	15484	12980	3	12850	20100	10200	10000	10200	10000	15437	151	1	1	20201	100	99	2124	100	10100	100	23367	23373	33226	0	25048	23353	10000	0	1310	2	17	2	2	15437	10096	10000	10100	15520	15564	15573	15570	15503
20204	15470	116	384	200	385	24998	0	15566	9599	25	20217	10208	10000	10100	10000	129947	728969	1	39	49	12553	15597	15514	12760	3	13054	20100	10200	10000	10200	10000	15417	142	1	1	20201	100	99	2126	100	10100	100	23436	23303	33511	0	25241	23124	10000	0	1310	2	16	2	1	15448	10123	10000	10100	15582	15547	15607	15436	15466
20204	15412	118	382	204	386	24826	0	15528	9519	25	20193	10190	10000	10100	10000	129948	732058	1	37	49	12525	15414	15578	12784	3	12910	20100	10200	10000	10200	10000	15508	147	1	1	20201	100	99	2058	100	10100	100	23335	23401	33247	0	25059	23236	10000	0	1310	2	16	2	2	15396	10108	10000	10100	15437	15561	15408	15570	15468
20204	15531	116	385	205	388	25048	0	15428	9604	25	20175	10208	10000	10100	10000	129029	726832	1	40	49	12398	15295	15470	12763	3	12971	20100	10200	10000	10200	10000	15498	153	1	1	20201	100	99	2034	100	10100	100	23389	23301	33240	0	24983	23394	10000	0	1310	2	16	2	2	15377	10105	10000	10100	15397	15521	15462	15527	15488
20204	15651	116	387	198	387	24984	0	15464	9412	25	20211	10226	10000	10100	10000	131135	724540	1	31	49	12527	15441	15532	12902	3	13090	20100	10200	10000	10200	10000	15467	149	1	1	20201	100	99	2038	100	10100	100	22964	23242	33381	0	24990	23565	10000	0	1310	2	16	2	2	15340	10108	10000	10100	15404	15551	15461	15369	15431
20204	15433	116	389	200	385	25038	0	15496	9493	25	20202	10226	10000	10100	10000	130919	723493	1	37	49	12507	15495	15519	12717	3	12985	20100	10200	10000	10200	10000	15446	154	1	1	20201	100	99	2087	100	10100	100	23237	23148	33019	0	24921	23389	10000	0	1310	2	16	2	2	15326	10132	10000	10100	15603	15436	15624	15370	15501

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5553

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15420	117	382	192	380	0	24917	15461	9662	25	20154	10127	10000	10010	10000	131039	722078	0	44	49	12473	15613	15606	12859	3	13022	20010	10020	10000	10020	10000	15630	150	1	1	20021	10	9	2063	10	10010	10	23188	23181	33219	0	24848	23085	10000	1271	1	16	1	1	15492	10114	10000	10010	15519	15608	15659	15574	15544
20024	15649	117	388	194	377	0	24913	15592	9765	25	20115	10115	10000	10010	10000	131758	730599	0	42	49	12352	15553	15482	12889	3	13082	20010	10020	10000	10020	10000	15563	151	1	1	20021	10	9	2098	10	10010	10	23123	23285	33195	0	25083	23189	10000	1270	1	16	1	1	15402	10129	10000	10010	15699	15625	15632	15654	15656
20024	15453	116	377	197	382	0	24912	15517	9468	25	20139	10142	10000	10010	10000	130046	729138	0	50	49	12465	15560	15527	12936	3	13072	20010	10020	10000	10020	10000	15434	150	1	1	20021	10	9	2209	10	10010	10	23202	22992	33057	0	25012	23365	10000	1270	1	16	1	1	15406	10132	10000	10010	15627	15464	15368	15690	15578
20024	15577	117	377	192	378	0	24981	15473	9605	25	20130	10136	10000	10010	10000	130934	724012	0	50	49	12555	15531	15516	12908	3	13033	20010	10020	10000	10020	10000	15579	151	2	1	20021	10	9	2064	10	10010	10	23320	23338	33058	0	25153	23178	10000	1270	1	16	1	1	15552	10120	10000	10010	15582	15608	15600	15540	15565
20024	15679	117	381	202	380	0	25007	15522	9631	25	20160	10157	10000	10010	10000	131299	725411	0	42	49	12503	15552	15643	12824	3	12986	20010	10020	10000	10020	10000	15609	149	1	1	20021	10	9	2095	10	10010	10	23096	23016	33292	0	24735	23111	10000	1270	1	16	1	1	15410	10117	10000	10010	15640	15669	15479	15589	15561
20024	15572	115	373	194	384	0	24988	15583	9695	25	20118	10154	10000	10010	10000	130354	728764	0	42	49	12433	15450	15599	12882	3	13102	20010	10020	10000	10020	10000	15517	150	1	1	20021	10	9	2199	10	10010	10	23180	23040	33379	0	24743	23342	10000	1270	1	16	1	1	15333	10093	10000	10010	15590	15540	15620	15494	15520
20024	15600	116	374	201	379	0	24978	15485	9525	25	20127	10151	10000	10010	10000	130839	731746	0	45	49	12499	15419	15482	12944	3	13037	20010	10020	10000	10020	10000	15627	152	1	1	20021	10	9	2059	10	10010	10	23157	23245	33222	0	24832	23242	10000	1270	1	16	1	1	15262	10123	10000	10010	15494	15628	15528	15448	15581
20024	15553	116	378	192	378	0	24708	15533	9662	25	20139	10166	10000	10010	10000	130280	722159	1	39	49	12425	15526	15663	12828	3	13058	20010	10020	10000	10020	10000	15475	148	1	1	20021	10	9	2037	10	10010	10	23149	23173	33293	0	25064	22941	10000	1270	1	16	1	1	15390	10111	10000	10010	15608	15603	15726	15519	15744
20024	15601	117	378	192	379	0	24680	15577	9596	25	20157	10145	10000	10010	10000	131024	724005	1	43	49	12700	15515	15613	12917	3	12985	20010	10020	10000	10020	10000	15438	147	1	1	20021	10	9	2116	10	10010	10	23231	23160	33187	0	24813	23049	10000	1270	1	16	1	1	15410	10165	10000	10010	15407	15481	15548	15550	15587
20024	15682	117	382	198	379	0	24923	15449	9396	25	20130	10160	10000	10010	10000	130081	726303	1	35	49	12536	15548	15511	12796	3	13119	20010	10020	10000	10020	10000	15406	152	1	1	20021	10	9	2015	10	10010	10	23013	23142	33203	0	24864	23205	10000	1270	1	16	1	1	15472	10171	10000	10010	15648	15554	15717	15540	15658

Test 3: throughput

Code:

  prfm plil3keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5486

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15468	116	293	146	294	0	0	23853	0	15494	9583	25	10100	100	10000	100	10009	500	725388	49	12393	15520	15551	14079	19	14698	10100	200	10008	200	10016	15455	12224	1	1	10201	100	99	2640	100	100	100	22224	22228	32140	2	23810	22216	10000	1	1	1	717	0	16	0	0	15429	0	10000	100	15540	15466	15416	15456	15490
10204	15472	116	293	150	290	0	0	23876	0	15362	9529	25	10100	100	10000	100	10000	500	723395	49	12430	15468	15545	14040	6	14285	10100	200	10016	200	10016	15455	12259	1	1	10201	100	99	2561	100	100	100	22257	22179	32156	0	23867	22231	10000	1	1	1	719	0	16	0	0	15348	0	10000	100	15501	15501	15556	15544	15428
10204	15451	116	294	147	290	0	0	23934	0	15497	9556	25	10100	100	10000	100	10000	500	728274	49	12476	15484	15468	14065	7	14253	10100	200	10008	200	10008	15481	12213	1	1	10201	100	99	2537	100	100	100	22182	22201	32148	0	23910	22273	10000	1	1	1	719	0	16	0	0	15320	0	10000	100	15548	15539	15453	15405	15501
10204	15478	115	293	146	290	0	0	23961	0	15445	9472	25	10100	100	10000	100	10000	500	727174	49	12471	15385	15575	14083	6	14193	10102	200	10008	200	10008	15443	12191	1	1	10201	100	99	2589	100	100	100	22165	22201	32194	0	23890	22157	10000	1	1	1	719	0	16	0	0	15355	0	10000	100	15507	15522	15442	15445	15432
10204	15377	116	290	146	292	0	0	23842	0	15515	9586	25	10100	100	10000	100	10000	500	724572	49	12417	15526	15546	14048	6	14213	10106	200	10016	200	10016	15362	12252	1	1	10201	100	99	2611	100	100	100	22230	22143	32223	0	23875	22299	10000	1	1	1	718	0	16	0	0	15303	0	10000	100	15450	15553	15465	15441	15466
10204	15508	116	290	146	292	0	0	23862	0	15416	9555	25	10100	100	10000	100	10006	500	723115	49	12417	15420	15546	14055	7	14130	10102	200	10008	200	10024	15500	12257	1	1	10201	100	99	2582	100	100	100	22190	22159	32228	0	23875	22212	10000	1	1	1	717	0	16	0	0	15401	0	10000	100	15505	15498	15488	15533	15469
10204	15465	116	293	144	291	0	0	23921	0	15528	9608	25	10100	100	10000	100	10000	500	727595	49	12374	15540	15437	14024	6	14166	10107	200	10008	200	10016	15488	12261	1	1	10201	100	99	2588	100	100	100	22160	22189	32209	0	23878	22172	10000	1	1	1	717	0	16	0	0	15397	0	10000	100	15400	15475	15504	15461	15473
10204	15486	116	293	146	293	0	0	23918	0	15458	9600	25	10100	100	10000	100	10000	500	724116	49	12415	15522	15490	14010	6	14219	10100	200	10016	200	10016	15423	15778	1	1	10201	100	99	2576	100	100	100	22175	22258	32262	0	23944	22275	10000	1	1	1	717	0	16	0	0	15373	0	10000	100	15525	15568	15549	15481	15408
10204	15533	116	294	145	290	0	0	23860	0	15486	9531	25	10100	100	10000	100	10005	500	721725	49	12502	15469	15501	14030	7	14230	10100	200	10008	200	10008	15467	12229	1	1	10201	100	99	2626	100	100	100	22186	22263	32268	0	23894	22209	10000	1	1	1	717	0	16	0	0	15363	0	10000	100	15486	15630	15732	15482	15517
10204	15521	116	291	148	292	0	0	23842	0	15439	9729	25	10100	100	10000	100	10010	500	727274	49	12463	15519	15477	14028	6	14250	10100	200	10016	200	10008	15431	12234	1	1	10201	100	99	2573	100	100	100	22231	22145	32192	0	23916	22194	10000	1	1	1	718	0	16	0	0	15444	0	10000	100	15540	15530	15546	15482	15473

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5486

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15516	117	314	158	315	0	24317	15494	9542	25	10010	10	10000	10	10000	50	723643	0	49	12459	15510	15447	13975	3	14176	10010	20	10000	20	10000	15500	15475	1	1	10021	10	9	2735	10	10	10	22546	22424	32536	24245	22461	10000	640	3	16	3	3	15337	10000	10	15470	15488	15532	15484	15505
10024	15529	115	309	158	311	0	24217	15489	9543	25	10010	10	10000	10	10000	50	723876	0	49	12315	15526	15505	14060	3	14190	10010	20	10000	20	10000	15442	15451	1	1	10021	10	9	2659	10	10	10	22607	22549	32442	24359	22529	10000	640	3	16	3	3	15356	10000	10	15503	15465	15421	15436	15398
10024	15445	115	310	157	313	1	24305	15497	9597	25	10010	10	10000	10	10000	50	722370	0	49	12347	15499	15452	14103	3	14253	10010	20	10000	20	10000	15489	15363	1	1	10021	10	9	2724	10	10	10	22493	22503	32483	24278	22543	10000	640	3	16	3	3	15333	10000	10	15510	15442	15496	15449	15539
10024	15467	116	309	156	311	0	24340	15482	9416	25	10010	10	10000	10	10000	50	724218	1	49	12310	15453	15437	14041	3	14109	10010	20	10000	20	10000	15492	15566	1	1	10021	10	9	2626	10	10	10	22525	22526	32514	24295	22512	10000	640	3	16	3	3	15372	10000	10	15565	15550	15389	15425	15509
10024	15483	116	312	156	314	0	24291	15415	9564	25	10010	10	10000	10	10000	50	728619	0	49	12354	15524	15461	14122	3	14133	10010	20	10000	20	10000	15444	15468	1	1	10021	10	9	2618	10	10	10	22526	22567	32624	24313	22454	10000	640	3	16	3	3	15345	10000	10	15421	15541	15408	15456	15441
10024	15469	116	309	159	312	0	24338	15444	9585	25	10010	10	10000	10	10000	50	725590	0	49	12358	15449	15513	14056	3	14285	10010	20	10000	20	10000	15414	15469	1	1	10021	10	9	2663	10	10	10	22447	22587	32495	24316	22527	10000	640	3	16	3	3	15329	10000	10	15371	15580	15559	15516	15476
10024	15832	117	308	160	311	0	24317	15471	9536	25	10010	10	10000	10	10000	50	725915	1	49	12383	15472	15493	14119	3	14198	10010	20	10000	20	10000	15481	15490	1	1	10021	10	9	2698	10	10	10	22512	22553	32538	24293	22461	10000	640	3	16	3	3	15440	10000	10	15518	15483	15499	15601	15471
10024	15516	116	313	156	309	2	24252	15500	9594	25	10010	10	10000	10	10000	50	722201	1	49	12387	15464	15485	14020	3	14116	10010	20	10000	20	10000	15418	15340	1	1	10021	10	9	2707	10	10	10	22470	22597	32538	24283	22575	10000	640	3	16	4	3	15404	10000	10	15445	15488	15455	15507	15414
10024	15428	115	310	156	310	0	24279	15541	9566	25	10010	10	10000	10	10000	50	725826	1	49	12441	15514	15438	14099	3	14286	10010	20	10000	20	10000	15462	15429	1	1	10021	10	9	2724	10	10	10	22569	22665	32550	24321	22575	10000	640	3	16	3	3	15369	10000	10	15461	15542	15555	15505	15527
10024	15437	116	312	159	319	0	24300	15426	9577	25	10010	10	10000	10	10000	50	721908	0	49	12360	15520	15510	14099	3	14232	10010	20	10000	20	10000	15446	15461	1	1	10021	10	9	2668	10	10	10	22574	22476	32529	24295	22545	10000	640	3	16	3	3	15327	10000	10	15488	15520	15527	15484	15465

PRFM (register, PLIL3KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations