Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STCLRL (32-bit)

Test 1: uops

Code:

  stclrl w0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.007

Integer unit issues: 1.007

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f1e1f223a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6061696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
730053301224612211261001010106004327940020625300410042000100020001113516934910492947803267733205313300010002000200040003262425971171001100010000200443210081001026200351032115896114761844240915542281039234438134353322891006162751555614974200010003295732565328053269432844
7300433062249119111810010071058933260711208763004100620001000200011027169301006492964003293433195312300010002000200040003270925771171001100010000200242210081001027200661222216298113141826738089482282740404434194743323651007163671454916147200010003274332778328043274532750
7300432901246117111911010081056783262910208143007100620001000200011111170431200492977403290733155313300010002000200040003276925501171001100010000200442210061001029200481222116437122031847740524462265139604433164552325271008160781479615118200010003279132846328093314232663
730043283724811711131111004115954326660021037300810072000100020001107816926900492966303263032745313300010002000200040003317625761171001100010000200422210091001008200691022215971122342847140475392320740094439184042323741008165751452115216200010003272432810327983318332702
7300433201249120102011110101059673267700206273009100720001000200011032169431400492963103280532644313300010002000200040003256525731171001100010000200232210071001029200471222215900120571830040776452296340864435194945323741006162931492015102200010003314032780327543277132649
7300432765244114111710010091159313264300206643006100720001000200011021169891100492953903260832780313300010002000200040003274325871171001100010000200242010081001016200661222215566118402846340245422269737634441185044324811008163081463915447200010003319732719329363268432572
73004327822451141113110100411611532515012060530041008200010002000110461697710004929742032616328383133000100020002000400032749259411710011000100002003402100710010082003512221157401210528515378310442323036984436154847324801004160591582614915200010003275732721327793312632814
730043270524811811141001010116178326980020535300610032000100020001096816876900492987503254332760313300010002000200040003277925771171001100010000200440310071001028200331022116456119792844639709412289738894438124043325251008163841447815217200010003275532765326243267233191
730043274724511911161111009106186326770020760300510052000100020001106916858900492954003256532688313300010002000200040003262625891171001100010000200330210081001009200371002215583114032842840504412274038384435144245323981007175351452714921200010003313133078327703279033115
7300432809245115011410010091160093261600206043008100420001000200011065168971000492965103271432757312300010002000200040003315425931171001100010000200332010091001018200641202116386121841821340319442273540444436193639323741006165241578515224200010003303133095330433283332871

Test 2: throughput

Code:

  stclrl w0, [x6]
  add x6, x6, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)090e191e1f202223293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
402077009152411110525622061004118070065184545395706225404762052020000201002000020454893321219113649669890700337007064508365027401002020020000302004000070069661120201100990100100001010010000010020218035721119875102331004618316015013120209048393512113101171169861202276620000201007007070070700707007070072
40204700695250000052282206100412167011128043930572832540607205372000020100200002044689332010701204966993070030700696450736502740100202002000030200400007006961112020110099010010000101001000001002023024931441987210177100351912021811320240149297384013101161169856206846620000201007007070084700707008571577
402047008552400002526222281004114070065201440345813225405902047420000201002000020457083320246112349669890700477006964507365027401002020020000302004000070069611120201100990100100001010010000010020174049012819871102171004111321022139202850592148480013101171169857203536620000201007007170070700707008570071
402047006952500010529912241084317670055193437405789825404222045620000201002000020453623320398113849669900700447006064507365027401002020020000302004000070069651120201100990100100001010010000010020187054116319871102401005817318010010320244093393496013101161169847202766620000201007008570070700847007070082
4020470069525000105241122310044172700542353494057055254036720393200002010020000204524533213561113496698907004570069645073650274010020200200003020040000700696111202011009901001000010100100000100202500447179198771023510028223214170125202110722112650013101161169856205106620000201007007070082700707007070070
40204700695250000052352159100551127005417543740567302540397203072000020100200002045278332101011314966989070034700696450836502740100202002000030200400007008161112020110099010010000101001000001002017206372061987210193100381432401811220241058196554013101161169856205316620000201007007070070700617007070070
402047006952500000530211871004312470065200339505688425403752056420000201002000020451163320676111049669890700307007664507365027401002020020000302004000070069611120201100990100100001010010000010020202055616519872102501000712314448124202450452114496013101161169856203316620000201007007070070700707006170070
40204700695250000052671174108468070054198328315762625404592056420000201002000020451933321245116749669890700297006964512365028401002020020000302004000070070651120201100990100100001010010000010020183052016319872102501003719319211288202230532119641013101161169856204626620000201007007070070700707008470070
4020470079525000005328217810963910070055216531365670125404992043820000201002000020453433320311110849669900700427007064518365041401002020020000302004000070070611120201100990100100001010010000010020187051816719871102241004515317770127202650641109479013101171169857205246620000201007007070076700717007070084
40204700695250000052922213108432047006918743829571272540403204172000020100200002045123332071511144966989070029700696452536504040100202002000030200400007006966112020110099010010000101001000001002019304832001987710179100061532282297202240441167545013101171169857204256620000201007007070070700707006170070

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)0309l2 tlb miss data (0b)0e0f191e1f202223293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)7bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
40027700945250001052610231101365018870054208334345706825403922032520000200102000020449213320970014949669897002970063645423650494001002002020000300204000070083611120021109010100001001010000102017504551541987310215100011611468216020243142280383012703163369861202786620000200107008970070700707007070070
4002470060535000005213118210039127005412123529571582540356203402000020010200002044530332104601564966989700307007864529365064400100200202000030020400007006961112002110901010000100101000010201660676144198711023310052223189812620245053265302012703163369847203329620000200107007070070700707007070070
4002470080525000005227220110057487005414912840570332540285203752000020010200002044502332047601064966989700307006964520365049400100200202000030020400007006961112002110901010000100101000010202310483158198721023110054273189409620201037278368012703163369856203256620000200107007070070700707007070070
4002470069525000005207113510176335270048150135245828825404022042220000200102000020446883320374015449669837002970069645293650484001002002020000300204000070074612120021109010100001001010000102014904821791987210204100341432312814720214060291368012703163369856202656620000200107007070070700647007070070
40024700695240000051871152100421727005414412733583452540196203832000020010200002044697332045501664966994700297006964529365050400100200202000030020400007006961112002110901010000100101000010202200663143198851020810057223198142135203290432112512012703153369856203046620000200107008570070700717007070064
400247006952500000525341661084716070069225326465790225402452025620000200102000020444183320469093496698970044700636453236504940010020020200003002040000700696111200211090101000010010100001020143040415219872101801000616317932106202220401147353012703164369856203686620000200107008070078700707007070070
40024700695250000052232193101444464700542162393457342254044820329200002001020000204450133212431163496698970027700696454436504740010020020200003002040000700696511200211090101000010010100001020198053117119875102151004023322132109203110552147416012703163469868202396620000200107007070070700707007070070
4002470069525000005268217810847120700731672363357199254029320307200002001020000204426533199070201496699470033700816453236504940010020020200003002040000700696111200211090101000010010100001020200046217119871102261002918119596121202251552153483012703163369872207516620000200107007070070700647007570085
40024700895240000052431184100538470067193138315684925403062063420000200102000020448603320273085496698970042700786452936504040010020020200003002040000700696111200211090101000010010100001020206056814919882102351003523319824147202730501105522012703164469869204716620000200107007070070700707007070070
400247006352500000519821551013641156700541742403656478254043920294200002001020000204435733205600105496698970029700636452336506240010120020200003002040000700696111200211090101000010010100001020253049715519872102841005120320722114202940701107465012703163369857202646620000200107007070562700707007070070

Test 3: throughput

Code:

  stclrl w0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0139

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
3020622022216500000110027423000012201520872019212550737274592321510100200008659578105263711482492170212201332207082154076216327301001841186610203200052020640009220157932111020110099100100001001000001002000003024270551000100171293706117015120320011171610843016002194062352705201002000010100220109220127220098220110220124
3020422019916490000112326931110002201160002015822550981281412296210100200008684017105254951483492170592201592201212154396216335301001753172610203200052020640009220127890111020110099100100001001000011002000003102667910139135315637279174690032001117221046522522219507170265090002000010100220154220152220134220117220102
30204220170164900000000277711100222013605020200925507612827022848101002000087561601052718215074921705322010322012521541662163333010022272343102002000020200400002201078881110201100991001000010010000010020000032182690810001001752837159171220203300111722100422252221941219427509101002000010100220119220149220135220131220176
3020422012916490000000027541010012201100322022742550579274152333510100200008559403105248231491492170332201252201152154291321632030100189918901020020000202004000022012782211102011009910010000100100000100200000021274701000000168603658317287023330011172299872252221948519327571101002000010100220156220108220100220114220096
3020422020616490000000027763000022200981052025232550108270972263910100200008788374105259371557492170662201052201072154106216347301001957199710200200002020040000220129882111020110099100100001001000001002000003002695210000001725237641168330143000111722106782242221940811827046141402000010100220145220153220114220119220124
3020422008716490000100027062010022201150602018692550680283252273310100200008975980105230101530492170652201552201312153796216348301001975213110200200002020040000220127874111020110099100100001001000001002000003221267061000000169793724217160119330011172210414225222194292022747110002000010100220113220106220128220110220122
302042202581649000000002756601001220134077202520255023626721237511010020000858123210525556153249217085220145220117215481621634730100187420011020020000202004000022010092611102011009910010000100100000100200000002702810000710169513700817031015300011172210489224222193641822757113002000010100220100220150220116220119220133
30204220184164900000010270241000122010201102022262550719276652316610100200008530963105255131540492170552201412201232155176216334301001822185310200200002020040000220157992111020110099100100001001000001002000003115273901000000175463668416705003300111722106182252221942517527591141012000010100220110220120220144220134220154
302042201301649000000002746811001220147005201963255041628119223161010020000872008610524805152649217047220155220149215339621635630100155517071024820000202004000022012990411102011009910010000100100000100200000023271011000050173153725617534018300011172210843225222193656528064101002000010100220116220124220136220164220134
30204220114165000000000273730100222013410320176225498082760622388101002000085654521052451714654921705722009722013121549462163293010016241766102002000020200400002200979761110201100991001000010010000010020000000268871000100171933692216988021290011172210650225222194095327804141402000010100220165220226220181220122220137

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0259

retire uop (01)cycle (02)03l2 tlb miss data (0b)0e0f191e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
30025220224164900003166410002202303015200250255291732966200621001020000107329721052428401358492172030220259220225215405321645930010118126100202000020020402252202496581110021109687501010000101000001020000272931593100002215694155721586100006401524931622219347032863662000010010220272220256220284220250220268
30024220239165000003154911002202882141520086625529303290720066100102000010683608105245471139449217183022024122022321537132164753001014314310020200002002040000220327648111002110943246101000010100000102000027283147010001021365414402145012527006401523721622219441332745662000010010220256220246220226220258220238
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3002422026916500000314091100220238213132017052552842328652007910010200001059637510525020113684921719702202472202692154363216551300101481501002020000200204000022029966011100221094162910100001010000010200002728315061000002148441461214170250016401516521622219391332809662000010010220288220232220270220256220262
30024220223165000003152311002202123141520149025528793282220074100102000010661023105253260132249217171022027122024121537532164323001013611310020200002002040000220253658111002110956182101000010100000102000027273165210001021646416192156312527006401525221622219402332782662000010010220292220212220268220222220280
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