Firestorm: BIC (register, 32-bit) measurements

Code:

  bic w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1022	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	84	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1153	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	1190	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	90	61	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	82	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	9	61	862	25	1000	1000	1000	16916	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  bic w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	9	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	441	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	1	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	12	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	0	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	1	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	642	0	0	9	39	3	4	9941	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	1	0	61	9863	25	10010	10010	10010	88784	1	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	6	61	9863	25	10010	10010	10010	88784	0	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	93	61	9863	25	10010	10010	10010	88784	0	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9863	25	10010	10010	10010	88784	0	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	4	9940	10000	10010	10036	10082	10036	10036	10036
10024	10035	76	0	0	61	9866	25	10010	10010	10010	88784	0	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	61	9863	25	10010	10010	10010	88784	1	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	61	9863	25	10010	10010	10010	88784	1	0	49	6955	10035	10035	8602	0	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	3	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	12	61	9863	25	10010	10010	10010	88784	1	0	49	6955	10035	10035	8602	0	3	8741	10012	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	1	0	640	0	0	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	120	61	9866	25	10010	10010	10010	88784	1	0	49	6955	10035	10035	8603	0	3	8742	10012	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	640	0	0	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  bic w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	82	9877	44	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	0	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10292	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	3	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	49	6955	10035	10035	8580	22	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	1	37	1	1	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	84	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	6	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	246	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 4: throughput

Count: 8

Code:

  bic w0, w8, w9
  bic w1, w8, w9
  bic w2, w8, w9
  bic w3, w8, w9
  bic w4, w8, w9
  bic w5, w8, w9
  bic w6, w8, w9
  bic w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13429	104	0	1	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	56	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	98	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	0	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	13386	100	0	18	35	25	80010	80010	80010	400050	2	1	49	10291	13371	13371	3330	3	3348	80010	80020	160838	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	2	19	2	5	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	35	25	80010	80010	80010	400050	3	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	4	19	5	5	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	35	25	80010	80010	80010	400050	3	1	49	10291	13371	13371	3330	3	3348	80010	80151	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	3	19	4	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	1	0	35	25	80010	80010	80010	400050	3	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	3	19	4	3	13368	80000	80010	13433	13372	13372	13372	13372
80024	13371	100	0	3	35	25	80010	80010	80010	400050	3	0	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	4	19	4	5	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	35	25	80010	80010	80010	400050	3	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	3	19	4	4	13368	80390	80010	13372	13372	13372	13372	13372
80024	13371	100	0	12	35	25	80010	80010	80010	400050	3	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	4	19	5	3	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	35	25	80010	80010	80010	536222	3	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	3	19	5	5	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	0	35	25	80010	80010	80010	400050	4	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	4	19	5	5	13368	80000	80010	13372	13372	13372	13372	13372
80024	13371	100	0	12	35	25	80010	80010	80010	400050	3	1	49	10291	13371	13371	3330	3	3348	80010	80020	160020	13371	39	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	3	19	4	4	13368	80000	80010	13372	13372	13372	13372	13372

BIC (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations