Firestorm: PRFM (register, PLDL2STRM) measurements

Code:

  prfm pldl2strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1614	12	34	17	33	0	2469	0	1616	911	25	1000	1000	1000	69305	1	1594	1584	1303	3	1482	1000	1000	1000	1558	1569	1	1	1001	248	2298	2292	3266	0	2449	2221	1000	73	1	16	1	1	1475	0	1000	1623	1609	1624	1615	1597
1004	1575	12	35	18	34	0	2438	0	1585	873	25	1000	1000	1000	70472	1	1587	1577	1316	3	1426	1000	1000	1000	1575	1596	1	1	1001	229	2297	2304	3280	0	2466	2278	1000	73	1	16	1	1	1487	0	1000	1572	1594	1615	1569	1632
1004	1624	12	32	17	34	0	2479	0	1576	880	25	1000	1000	1000	68999	1	1563	1597	1317	3	1467	1000	1000	1000	1573	1569	1	1	1001	235	2304	2281	3294	2	2440	2249	1000	73	1	16	1	1	1510	1	1000	1603	1577	1562	1569	1621
1004	1616	12	34	17	33	0	2432	0	1596	880	25	1000	1000	1000	69337	1	1596	1571	1278	3	1452	1000	1000	1000	1575	1544	1	1	1001	244	2282	2260	3289	0	2448	2279	1000	73	1	16	1	1	1479	0	1000	1617	1578	1599	1583	1584
1004	1589	12	33	17	34	0	2557	0	1552	856	25	1000	1000	1000	71745	1	1596	1640	1283	3	1436	1000	1000	1000	1588	1591	1	1	1001	240	2273	2262	3282	0	2422	2278	1000	73	1	16	1	1	1502	0	1000	1607	1616	1602	1564	1599
1004	1578	12	34	16	34	0	2444	0	1576	886	25	1000	1000	1000	69791	1	1565	1617	1312	3	1450	1000	1000	1000	1587	1558	1	1	1001	239	2255	2287	3299	0	2453	2310	1000	73	1	16	1	1	1501	0	1000	1614	1583	1601	1572	1596
1004	1588	12	34	17	33	0	2441	0	1605	869	25	1000	1000	1000	69862	1	1593	1624	1279	3	1460	1000	1000	1000	1595	1573	1	1	1001	251	2260	2270	3258	0	2442	2284	1000	73	1	16	1	1	1508	0	1000	1613	1590	1625	1597	1596
1004	1566	12	34	16	34	0	2458	0	1599	887	25	1000	1000	1000	69619	1	1603	1575	1309	3	1484	1000	1000	1000	1599	1548	1	1	1001	243	2262	2300	3297	0	2443	2277	1000	73	1	16	1	1	1553	0	1000	1615	1577	1611	1611	1572
1004	1606	12	33	18	34	0	2429	0	1604	901	25	1000	1000	1000	67982	1	1592	1621	1287	3	1421	1000	1000	1000	1569	1615	1	1	1001	231	2268	2285	3284	0	2443	2264	1000	73	1	16	1	1	1495	0	1000	1598	1568	1593	1597	1628
1004	1620	12	32	17	33	0	2477	88	1592	882	25	1000	1000	1000	69284	1	1603	1614	1269	3	1484	1000	1000	1000	1571	1566	1	1	1001	221	2266	2284	3263	0	2489	2255	1000	73	1	16	1	1	1486	0	1000	1603	1573	1597	1602	1611

Test 2: throughput

Code:

  prfm pldl2strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5815

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15838	117	333	187	336	24201	15860	9858	25	20226	10196	10000	10100	10000	133738	744073	0	46	49	12710	15694	15734	13129	3	13217	20100	10200	10000	10200	10000	15679	149	1	1	20201	100	99	2592	100	10100	100	22690	22720	32860	0	0	24486	22739	10000	1310	1	16	1	1	15708	10096	10000	10100	15768	15739	15869	15663	15804
20204	15855	119	336	177	334	24443	15634	9783	25	20214	10190	10000	10100	10000	131373	740046	0	35	49	12774	15685	15705	13066	3	13186	20100	10200	10000	10200	10000	15830	157	1	1	20201	100	99	2491	100	10100	100	22654	22626	32613	0	0	24419	22728	10000	1310	1	16	1	1	15804	10102	10000	10100	15834	15898	15934	15807	15796
20204	15734	119	343	178	347	24286	15769	9868	25	20220	10226	10000	10100	10000	133143	740675	0	32	49	12693	15742	15786	13099	3	13406	20100	10200	10000	10200	10000	15801	149	1	1	20201	100	99	2404	100	10100	100	22858	22685	32533	0	0	24401	22674	10000	1310	1	16	1	1	15684	10111	10000	10100	15869	15892	15796	15725	15787
20204	15856	118	334	179	340	24384	15789	9835	25	20211	10187	10000	10100	10000	133516	738364	1	40	49	12723	15868	15911	13173	3	13293	20100	10200	10000	10200	10000	15730	145	1	1	20201	100	99	2439	100	10100	100	22691	22767	32854	0	0	24465	22636	10000	1310	1	16	1	1	15654	10117	10000	10100	15776	15774	15717	15738	15726
20204	15951	118	337	172	339	24349	15884	9864	25	20235	10223	10000	10100	10000	134282	739500	1	37	49	12763	15916	15891	13051	3	13191	20100	10200	10000	10200	10000	15709	157	1	1	20201	100	99	2453	100	10100	100	22800	22674	32626	0	0	24464	22718	10000	1310	1	41	1	1	15559	10262	10000	10100	15738	15861	15810	15856	15798
20204	15729	118	338	181	336	24720	15782	9860	25	20226	10181	10000	10100	10000	133292	736483	0	41	49	12790	15780	15710	13061	3	13254	20100	10200	10000	10200	10000	15724	150	1	1	20201	100	99	2588	100	10100	100	22737	22839	32671	0	0	24388	22656	10000	1310	1	17	1	1	15794	10099	10000	10100	15851	15936	15831	15731	15848
20204	15666	118	338	176	346	24539	15682	9860	25	20220	10223	10000	10100	10000	132664	739298	0	36	49	12683	15819	15782	13042	3	13185	20100	10200	10000	10200	10000	15892	151	1	1	20201	100	99	2441	100	10100	100	22738	22866	32578	0	0	24219	22702	10000	1310	1	16	1	1	15711	10099	10000	10100	15854	15788	15652	15740	15722
20204	15864	118	339	177	339	24573	15651	9817	25	20217	10217	10000	10100	10000	133577	737558	0	32	49	12726	15598	15743	13072	3	13250	20100	10200	10000	10200	10000	15653	150	1	1	20201	100	99	2535	100	10100	100	22665	22873	32707	0	0	24338	22759	10000	1310	1	16	1	1	15617	10105	10000	10100	15878	15803	15768	15903	15715
20204	15723	119	334	180	338	24401	15806	9894	25	20208	10196	10000	10100	10000	134503	735745	0	44	49	12687	15774	15763	13150	3	13160	20100	10200	10000	10200	10000	15745	159	1	1	20201	100	99	2546	100	10100	100	22557	22592	32730	0	0	24316	22752	10000	1310	1	16	1	1	15629	10108	10000	10100	15873	15777	15885	15717	15861
20204	15795	119	338	182	335	24379	15763	9718	25	20214	10217	10000	10100	10000	135083	739294	0	31	49	12751	15682	15872	13069	3	13180	20100	10200	10000	10200	10000	15792	160	1	1	20201	100	99	2397	100	10100	100	22678	22626	32809	0	0	24514	22792	10000	1310	1	16	1	1	15777	10096	10000	10100	15743	15737	15959	15794	15707

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5784

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15568	119	350	182	346	0	24819	1	15850	9693	25	20124	10118	10000	10010	10000	134422	742370	47	49	12704	15779	15857	13043	3	13361	20010	10020	10000	10020	10000	15838	176	1	1	20021	10	9	2507	10	10010	10	22787	22711	32788	0	24429	22724	10000	0	1272	3	16	4	3	15600	10150	10000	10010	15729	15748	15760	15746	15755
20024	15752	118	346	183	344	0	24322	1	15775	9746	25	20142	10145	10000	10010	10000	134407	736105	40	49	12644	15720	15788	13106	3	13244	20010	10020	10000	10020	10000	15894	152	1	1	20021	10	9	2359	10	10010	10	22697	22768	32783	0	24334	22604	10000	0	1272	2	15	2	3	15773	10150	10000	10010	15812	15811	15725	15782	15876
20024	15845	118	345	180	347	0	24935	1	15861	9837	25	20148	10142	10000	10010	10000	133598	740181	40	49	12716	15846	15817	13165	3	13174	20010	10020	10000	10020	10000	15715	152	1	1	20021	10	9	2540	10	10010	10	22671	22784	32816	0	24435	22858	10000	0	1272	3	16	2	3	15703	10144	10000	10010	15648	15760	15784	15811	15811
20024	15691	118	349	183	343	0	24652	1	15811	9793	25	20148	10124	10000	10010	10000	133582	741782	41	49	12685	15820	15747	13084	3	13453	20010	10020	10000	10020	10000	15723	144	1	1	20021	10	9	2386	10	10010	10	22635	22721	32579	0	24469	22561	10000	0	1272	2	16	2	3	15843	10123	10000	10010	15784	15839	15923	15927	15806
20024	15779	118	342	179	346	0	24505	1	15698	9811	25	20172	10151	10000	10010	10000	133989	740185	50	49	12723	15770	15690	13178	3	13170	20010	10020	10000	10020	10000	15707	153	1	1	20021	10	9	2482	10	10010	10	22916	22837	32751	0	24487	22719	10000	0	1272	2	16	2	3	15651	10129	10000	10010	15856	15859	15974	15768	15796
20024	15707	119	343	174	347	0	24938	1	15724	9797	25	20124	10145	10000	10010	10000	132576	735103	39	49	12680	15724	15931	13081	3	13260	20010	10020	10000	10020	10000	15744	156	1	1	20021	10	9	2454	10	10010	10	23136	22759	32688	0	24404	22649	10000	0	1272	3	16	3	2	15614	10147	10000	10010	15782	15770	15814	15808	15766
20024	15840	117	346	181	345	0	24329	1	15720	9937	25	20139	10115	10000	10010	10000	134205	737712	49	49	12600	15792	15935	13115	3	13250	20010	10020	10000	10020	10000	15744	176	1	1	20021	10	9	2571	10	10010	10	22891	22714	32781	0	24287	22578	10000	0	1272	2	16	2	3	15758	10129	10000	10010	15671	15649	15811	15938	15795
20024	15718	118	349	183	348	0	24364	1	15796	9973	25	20142	10154	10000	10010	10000	134176	737084	38	49	12710	15665	15638	13108	3	13278	20010	10020	10000	10020	10000	15683	152	1	1	20021	10	9	2519	10	10010	10	22722	22730	32752	0	24469	22918	10000	0	1272	3	16	2	3	15670	10123	10000	10010	15682	15740	15673	15850	15729
20024	15726	118	342	181	347	0	24481	1	15822	9685	25	20121	10133	10000	10010	10000	133702	734615	51	49	12819	15758	15831	13066	3	13314	20010	10020	10000	10020	10000	15842	152	1	1	20021	10	9	2481	10	10010	10	22657	22709	32744	0	24479	22750	10000	0	1272	2	16	3	3	15579	10120	10000	10010	15849	15770	15785	15763	15860
20024	15740	118	345	181	345	0	24338	1	15808	9826	25	20181	10151	10000	10010	10000	132551	733369	50	49	12675	15844	15695	13026	3	13357	20010	10020	10000	10020	10000	15826	149	1	1	20021	10	9	2517	10	10010	10	22755	22827	32695	0	24342	23052	10000	0	1272	3	15	4	3	15729	10238	10000	10010	15930	15832	15795	15751	15724

Test 3: throughput

Code:

  prfm pldl2strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5424

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15455	115	308	153	309	24345	15368	9416	25	10100	100	10000	100	10001	500	719221	1	49	12378	15399	15340	14031	7	14122	10100	200	10016	200	10016	15404	12199	1	1	10201	100	99	2532	100	100	100	22438	22430	32492	0	24316	22464	10000	1	1	1	718	0	16	15295	10000	100	15477	15441	15363	15396	15504
10204	15348	115	308	153	308	24693	15433	9414	25	10100	100	10000	100	10003	500	722764	1	49	12326	15375	15378	14032	6	14122	10100	200	10008	200	10008	15374	12218	1	1	10201	100	99	2519	100	100	100	22587	22451	32501	0	24216	22414	10000	1	1	1	718	2	16	15356	10000	100	15406	15382	15398	15473	15475
10204	15451	115	309	155	305	24256	15448	9512	25	10167	100	10020	100	10000	500	719493	1	49	12278	15372	15434	13960	7	14051	10104	200	10024	200	10008	15416	12214	1	1	10201	100	99	2548	100	100	100	22540	22548	32468	0	24187	22393	10000	1	1	1	719	0	16	15265	10000	100	15475	15459	15403	15284	15439
10204	15432	115	304	153	304	24277	15380	9409	25	10100	100	10000	100	10000	500	721100	1	49	12224	15468	15491	13934	7	14189	10100	200	10016	200	10008	15429	12212	1	1	10201	100	99	2469	100	100	100	22530	22496	32533	0	24261	22567	10000	1	1	1	719	0	16	15344	10000	100	15384	15489	15454	15387	15474
10204	15435	115	310	155	306	24267	15414	9432	25	10100	100	10000	100	10002	500	720763	1	49	12404	15400	15397	14046	6	14075	10103	200	10008	200	10008	15360	12262	1	1	10201	100	99	2497	100	100	100	22448	22399	32462	0	24228	22419	10000	1	1	1	717	0	16	15270	10000	100	15396	15447	15460	15473	15456
10204	15441	115	308	151	307	24268	15480	9450	25	10100	100	10000	100	10000	500	722009	1	49	12386	15415	15463	13917	6	14066	10100	200	10008	200	10008	15312	12243	1	1	10201	100	99	2517	100	100	100	22460	22477	32496	0	24146	22471	10000	1	1	1	717	0	16	15311	10000	100	15387	15372	15440	15449	15455
10204	15473	115	307	154	307	24224	15359	9442	25	10100	100	10000	100	10000	500	722716	0	49	12446	15395	15316	14003	7	14062	10100	200	10008	200	10008	15378	12243	1	1	10201	100	99	2585	100	100	100	22484	22419	32516	0	24247	22390	10000	1	1	1	717	0	16	15396	10000	100	15394	15440	15403	15475	15457
10204	15476	116	308	154	306	24217	15437	9477	25	10100	100	10000	100	10007	500	720027	0	49	12273	15480	15355	13957	6	14177	10107	200	10008	200	10008	15365	12166	1	1	10201	100	99	2496	100	100	100	22573	22494	32461	0	24163	22489	10000	1	1	1	718	0	16	15274	10000	100	15514	15408	15398	15391	15428
10204	15451	115	307	154	308	24161	15467	9549	25	10100	100	10000	100	10004	500	722704	1	49	12361	15463	15365	13957	6	14171	10100	200	10008	200	10008	15457	12147	1	1	10201	100	99	2550	100	100	100	22526	22515	32506	0	24204	22482	10000	1	1	1	717	0	16	15380	10000	100	15397	15418	15406	15428	15483
10204	15459	116	307	154	308	24273	15411	9431	25	10100	100	10000	100	10000	500	722338	1	49	12422	15422	15469	13956	6	14172	10106	200	10016	200	10016	15357	12220	1	1	10201	100	99	2455	100	100	100	22498	22492	32446	0	24294	22487	10000	1	1	1	718	0	16	15333	10000	100	15407	15449	15414	15533	15431

1000 unrolls and 10 iterations

Result (median cycles for code): 1.4032

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	14047	105	429	421	427	27248	13970	8287	25	10010	10	10000	10	10000	50	655550	0	49	10918	14006	14011	12625	3	12787	10010	20	10000	20	10000	14081	14037	1	1	10021	10	9	49	10	10	10	25455	25515	35520	27341	25478	10000	640	7	16	2	2	13964	10000	10	14100	14087	13983	14018	14032
10024	14018	105	426	425	428	27283	13996	8240	25	10010	10	10000	10	10000	50	655502	0	49	10943	14048	14031	12607	3	12757	10010	20	10000	20	10000	14006	14048	1	1	10021	10	9	65	10	10	10	25515	25622	35496	27335	25518	10000	640	2	16	2	2	13968	10000	10	14081	14035	13975	13994	14060
10024	14026	105	425	422	424	27224	14010	8311	25	10010	10	10000	10	10000	50	655550	0	49	10937	14042	14011	12603	3	12765	10010	20	10000	20	10000	14049	14042	1	1	10021	10	9	39	10	10	10	25595	25491	35492	27247	25503	10000	640	2	16	2	2	13944	10000	10	14048	14029	14008	13993	14040
10024	14008	105	427	420	429	27315	14082	8223	25	10010	10	10000	10	10000	50	655502	0	49	10965	14016	14035	12635	3	12749	10010	20	10000	20	10000	14117	14020	1	1	10021	10	9	48	10	10	10	25471	25492	35559	27248	25481	10000	640	2	16	2	2	13950	10000	10	14054	13998	14048	14043	13983
10024	14039	104	428	421	428	27354	14008	8250	25	10010	10	10000	10	10000	50	656972	0	49	10944	14022	14009	12560	3	12773	10010	20	10000	20	10000	14062	14045	1	1	10021	10	9	66	10	10	10	25468	25386	35522	27332	25479	10000	640	2	16	2	2	13969	10000	10	14043	14036	14018	14004	14027
10024	14032	105	426	422	426	27248	14019	8246	25	10010	10	10000	10	10000	50	655774	0	49	10933	14070	14070	12643	3	12757	10010	20	10000	20	10000	14033	14070	1	1	10021	10	9	67	10	10	10	25416	25559	35526	27231	25459	10000	640	2	16	2	2	13953	10000	10	14012	14036	13998	13991	14061
10024	14059	105	426	421	428	27363	14037	8234	25	10010	10	10000	10	10000	50	655178	0	49	11000	14018	14044	12642	3	12796	10010	20	10000	20	10000	13998	14042	1	1	10021	10	9	27	10	10	10	25531	25445	35552	27164	25488	10000	640	2	16	2	2	13967	10000	10	14051	14019	14056	14036	14040
10024	14043	105	427	426	426	27356	13986	8212	25	10010	10	10000	10	10000	50	653821	0	49	10975	14043	14005	12584	3	12799	10010	20	10000	20	10000	14003	14041	1	1	10021	10	9	48	10	10	10	25500	25458	35473	27301	25546	10000	640	2	16	2	2	13927	10000	10	14041	14043	14011	14019	14035
10024	14060	105	427	422	427	27317	14020	8226	25	10010	10	10000	10	10000	50	658319	0	49	10927	14030	13995	12656	3	12739	10010	20	10000	20	10000	14108	14026	1	1	10021	10	9	27	10	10	10	25558	25515	35561	27356	25478	10000	640	2	16	2	2	13997	10000	10	14036	14084	14038	14017	14028
10024	14031	105	428	424	429	27248	13957	8240	25	10010	10	10000	10	10000	50	655817	0	49	10999	14008	14018	12655	3	12765	10010	20	10000	20	10000	13996	14032	1	1	10021	10	9	75	10	10	10	25546	25536	35565	27191	25416	10000	640	2	16	2	2	13949	10000	10	14061	13993	14051	13999	13998

PRFM (register, PLDL2STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations