Firestorm: PRFM (register, PLDL1KEEP) measurements

Code:

  prfm pldl1keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1608	12	35	17	36	2454	15	1608	924	25	1000	1000	1000	69521	1	1602	1602	1304	3	1433	1000	1000	1000	1601	1592	1	1	1001	239	2265	2263	3294	0	2445	2276	1000	73	1	16	1	1	1491	1000	1617	1606	1598	1608	1620
1004	1627	12	34	17	33	2466	53	1600	865	25	1000	1000	1000	70530	1	1604	1581	1342	3	1459	1000	1000	1000	1588	1611	1	1	1001	255	2287	2315	3292	0	2430	2263	1000	73	1	16	1	1	1496	1000	1611	1625	1607	1618	1628
1004	1615	12	35	19	34	2439	10	1570	901	25	1000	1000	1000	69097	0	1583	1601	1279	3	1473	1000	1000	1000	1596	1619	1	1	1001	253	2264	2308	3291	0	2460	2283	1000	73	1	16	1	1	1491	1000	1624	1597	1581	1615	1641
1004	1616	12	32	17	35	2475	11	1643	893	25	1000	1000	1000	70465	1	1585	1595	1301	3	1481	1000	1000	1000	1614	1571	1	1	1001	239	2288	2279	3274	0	2464	2257	1000	73	1	16	1	1	1510	1000	1617	1591	1592	1593	1639
1004	1627	12	34	18	33	2484	8	1595	866	25	1000	1000	1000	69918	1	1576	1604	1333	3	1598	1000	1000	1000	1602	1583	1	1	1001	281	2281	2295	3283	0	2460	2308	1000	73	1	16	1	1	1505	1000	1606	1598	1609	1599	1710
1004	1627	12	36	17	35	2468	10	1596	868	25	1000	1000	1000	70684	1	1593	1618	1303	3	1462	1000	1000	1000	1592	1588	1	1	1001	256	2263	2287	3284	0	2453	2276	1000	73	1	16	1	1	1524	1000	1616	1611	1576	1609	1599
1004	1592	12	34	19	33	2455	52	1577	909	25	1000	1000	1000	74336	1	1588	1566	1315	3	1468	1000	1000	1000	1597	1610	1	1	1001	265	2250	2308	3310	0	2445	2251	1000	73	1	16	1	1	1501	1000	1599	1612	1590	1619	1626
1004	1598	12	35	18	34	2480	7	1565	894	25	1000	1000	1000	68831	1	1597	1619	1310	3	1499	1000	1000	1000	1594	1601	1	1	1001	256	2291	2310	3299	0	2445	2294	1000	73	1	16	1	1	1491	1000	1617	1606	1598	1609	1620
1004	1627	12	34	17	34	2486	55	1608	891	25	1000	1000	1000	68956	1	1596	1618	1324	3	1453	1000	1000	1000	1591	1583	1	1	1001	247	2257	2266	3294	0	2451	2273	1000	73	1	16	1	1	1535	1000	1615	1622	1599	1582	1620
1004	1641	12	32	17	36	2434	7	1582	870	25	1000	1000	1000	69803	1	1606	1631	1282	3	1479	1000	1000	1000	1576	1569	1	1	1001	255	2295	2272	3276	0	2467	2294	1000	73	1	16	1	1	1498	1000	1599	1620	1584	1593	1589

Test 2: throughput

Code:

  prfm pldl1keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5525

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15615	117	381	198	382	0	25107	7533	15491	9661	25	20244	10211	10000	10100	10000	129723	732094	1	37	49	12438	15459	15519	12746	3	12942	20343	10200	10000	10200	10000	15519	152	1	1	20201	100	99	2197	100	10100	100	23068	23313	33330	0	0	25011	23358	10000	1310	2	16	2	2	15527	10120	10000	10100	15516	15536	15502	15416	15571
20204	15705	116	385	198	381	0	25226	10560	15519	9644	25	20208	10217	10000	10100	10000	129128	726458	1	31	49	12460	15539	15482	12851	3	13041	20100	10200	10000	10200	10000	15550	151	1	1	20201	100	99	2206	100	10100	100	23255	23313	33245	0	0	24949	23432	10000	1310	2	17	2	2	15448	10102	10000	10100	15501	15509	15601	15617	15614
20204	15505	116	389	202	379	0	24911	7605	15538	9594	25	20193	10223	10000	10100	10000	130054	729289	1	42	49	12488	15536	15487	12844	3	12833	20100	10200	10000	10200	10000	15531	154	1	1	20201	100	99	2071	100	10100	100	23330	23303	33190	0	0	24969	23223	10000	1310	2	16	2	2	15426	10126	10000	10100	15448	15518	15626	15526	15530
20204	15525	115	382	193	377	0	24816	7669	15341	9692	25	20196	10211	10000	10100	10000	131567	728441	1	34	49	12431	15412	15502	12829	3	13083	20100	10200	10000	10200	10000	15419	154	1	1	20201	100	99	2149	100	10100	100	23302	23281	33224	0	0	25069	23093	10000	1310	2	16	2	2	15408	10111	10000	10100	15502	15587	15574	15638	15485
20204	15671	116	383	191	383	0	25307	7746	15570	9609	25	20220	10211	10000	10100	10000	130557	725052	1	37	49	12401	15454	15504	12762	3	13069	20100	10200	10000	10200	10000	15455	148	1	1	20201	100	99	2202	100	10100	100	23416	23368	33203	0	0	25152	23200	10000	1310	2	17	2	2	15381	10108	10000	10100	15474	15487	15444	15392	15580
20204	15491	117	383	195	376	0	24948	7696	15521	9512	25	20175	10217	10000	10100	10000	130176	721805	1	26	49	12958	15647	15542	12821	3	12841	20100	10200	10000	10200	10000	15458	151	1	1	20201	100	99	2163	100	10100	100	23315	23363	33347	0	0	25045	23191	10000	1310	2	16	2	2	15385	10102	10000	10100	15416	15616	15527	15521	15540
20204	15544	118	378	203	379	0	24945	7632	15496	9594	25	20220	10181	10000	10100	10000	130932	730009	1	38	49	12372	15478	15578	12778	3	13009	20100	10200	10000	10200	10000	15592	152	1	1	20201	100	99	2159	100	10100	100	23479	23318	33221	0	0	24945	23269	10000	1310	2	16	2	2	15354	10099	10000	10100	15573	15475	15446	15429	15609
20204	15495	116	381	193	379	0	25200	7676	15590	9499	25	20223	10181	10000	10100	10000	129308	730742	1	37	49	12438	15553	15530	12777	3	12945	20100	10200	10000	10200	10000	15485	146	1	1	20201	100	99	2184	100	10100	100	23223	23250	33124	0	0	24927	23147	10000	1310	2	16	2	2	15525	10132	10000	10100	15465	15622	15527	15526	15611
20204	15545	116	374	198	379	0	24967	7756	15490	9546	25	20205	10238	10000	10100	10000	130889	730679	1	32	49	12550	15527	15537	12897	3	13040	20100	10200	10000	10200	10000	15542	138	1	1	20201	100	99	2148	100	10100	100	23232	23298	33453	0	0	25061	23119	10000	1310	2	17	2	2	15225	10120	10000	10100	15657	15511	15494	15540	15620
20204	15507	116	383	197	381	0	24869	7580	15520	9638	25	20217	10214	10000	10100	10000	130586	727977	1	36	49	12435	15585	15495	12754	3	13066	20100	10200	10000	10200	10000	15527	152	1	1	20201	100	99	2110	100	10100	100	23272	23435	33301	0	0	25129	23159	10000	1310	2	16	2	2	15328	10123	10000	10100	15593	15532	15589	15427	15538

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5621

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15473	117	0	360	197	0	360	0	0	24945	0	10260	15521	9614	25	20157	10136	10000	10010	10000	132175	724342	0	47	49	12508	15665	15627	12823	3	13105	20010	10020	10000	10020	10000	15446	157	1	1	20021	10	9	2327	10	10010	10	23056	22946	33069	0	0	24994	22921	10000	0	1270	1	16	1	1	15465	10120	10000	10010	15692	15694	15661	15630	15513
20024	15624	117	0	364	194	0	362	0	0	24640	0	10442	15528	9483	25	20139	10142	10000	10010	10000	132196	727660	0	44	49	12500	16191	15711	12875	3	13070	20010	10020	10000	10020	10113	15591	146	2	1	20021	10	9	2158	10	10010	10	22931	22990	33126	0	0	24642	23096	10000	0	1270	1	16	1	1	15453	10150	10000	10010	15511	15648	15594	15566	15611
20024	15683	117	0	366	192	0	362	1	0	24849	0	10433	15531	9588	25	20118	10121	10000	10010	10000	131256	725594	0	49	49	12479	15614	15611	12722	3	13057	20010	10020	10000	10020	10000	15624	158	1	1	20021	10	9	2346	10	10010	10	23157	22989	33104	0	0	24702	23077	10000	0	1270	1	16	1	1	15400	10135	10000	10010	15557	15675	15572	15691	15555
20024	15584	117	0	365	193	0	359	0	0	24657	0	10329	15694	9577	25	20127	10139	10000	10010	10000	130359	729068	0	43	49	12396	15649	15534	12878	3	13162	20010	10020	10000	10020	10000	15599	155	1	1	20021	10	9	2094	10	10010	10	22841	22893	33287	0	0	24644	22934	10000	0	1270	1	16	1	1	15411	10147	10000	10010	15533	15733	15618	15520	15653
20024	15543	118	0	363	201	0	371	0	0	24742	0	7261	15480	9703	25	20142	10133	10000	10010	10000	130833	724702	0	45	49	12543	15624	15528	12931	3	13130	20010	10020	10000	10020	10000	15556	158	1	1	20021	10	9	2337	10	10010	10	22993	23191	32971	0	0	24768	23066	10000	0	1270	1	16	1	1	15570	10135	10000	10010	15569	15675	15531	15556	15531
20024	15632	117	0	362	190	0	360	0	0	24900	0	10371	15625	9634	25	20148	10133	10000	10010	10000	130553	728716	0	42	49	12459	15554	15609	13138	3	13184	20010	10020	10000	10020	10000	15588	156	1	1	20021	10	9	2171	10	10010	10	23136	22898	33244	0	0	24739	23008	10000	0	1270	1	16	1	1	15525	10147	10000	10010	15599	15473	15868	15566	15542
20024	15482	116	0	362	199	0	370	0	0	24835	0	10243	15616	9642	25	20118	10166	10000	10010	10000	131304	731478	0	41	49	12467	15532	15542	12907	3	13067	20010	10020	10000	10020	10000	15634	146	1	1	20021	10	9	2254	10	10010	10	23109	23112	33062	0	0	24747	23254	10000	0	1270	1	16	1	1	15483	10141	10000	10010	15627	15613	15660	15546	15690
20024	15578	116	0	366	196	0	364	0	0	24828	0	10305	15613	9571	25	20166	10124	10000	10010	10000	132029	731766	0	52	49	12450	15574	15682	12960	3	12933	20010	10020	10000	10020	10000	15561	165	1	1	20021	10	9	2247	10	10010	10	23052	23105	33006	0	0	24940	23074	10000	0	1270	1	16	1	1	15440	10144	10000	10010	15519	15592	15592	15571	15669
20024	15542	116	0	367	195	0	367	0	0	24710	0	10342	15627	9529	25	20127	10142	10000	10010	10000	132259	722217	0	50	49	12515	15565	15587	12966	3	13159	20010	10020	10000	10020	10000	15543	146	1	1	20021	10	9	2349	10	10010	10	23050	23220	33121	0	0	24881	22856	10000	0	1270	1	16	1	1	15489	10117	10000	10010	15542	15505	15618	15649	15633
20024	15527	117	0	361	192	0	368	0	0	24715	0	10266	15634	9655	25	20130	10151	10000	10010	10000	131077	742026	0	41	49	12561	15501	15490	12837	3	13241	20010	10020	10000	10020	10000	15608	329	1	1	20021	10	9	2337	10	10010	10	23003	23047	32917	0	0	24878	23013	10000	0	1270	1	16	1	1	15525	10117	10000	10010	15680	15537	15684	15589	15771

Test 3: throughput

Code:

  prfm pldl1keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5423

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15436	116	330	171	328	24605	505	15368	9479	25	10100	100	10000	100	10000	500	715137	49	12614	15424	15472	14041	6	14094	10100	200	10000	200	10000	15294	12201	1	1	10201	100	99	2555	100	100	100	22755	22681	32908	0	24625	22828	10000	1	1	1	722	2	24	2	2	15248	10000	100	15406	15390	15374	15420	15378
10204	15379	115	333	166	328	24484	486	15419	9519	25	10100	100	10000	100	10000	500	727717	49	12228	15323	15453	13935	6	14109	10100	200	10000	200	10000	15383	12192	1	1	10201	100	99	2612	100	100	100	22865	22874	32745	0	24643	22848	10000	1	1	1	722	2	24	2	2	15405	10000	100	15413	15437	15423	15352	15414
10204	15505	116	330	170	333	24550	508	15401	9528	25	10100	100	10000	100	10000	500	724771	49	12281	15433	15501	13891	6	14158	10100	202	10119	200	10000	15455	12170	1	1	10201	100	99	2601	100	100	100	22820	22819	32828	1	24684	22800	10000	1	1	1	722	2	24	2	2	15318	10000	100	15397	15362	15383	15469	15436
10204	15360	116	328	172	337	24534	499	15433	9507	25	10100	100	10000	100	10000	500	720057	49	12359	15441	15518	13921	6	14056	10100	200	10000	200	10000	15395	12249	1	1	10201	100	99	2621	100	100	100	22731	22706	32818	0	24630	22783	10000	1	1	1	722	2	24	2	2	15257	10000	100	15480	15450	15363	15290	15404
10204	15395	116	334	166	329	24629	500	15373	9471	25	10100	100	10000	100	10000	500	725526	49	12339	15428	15454	13981	6	14179	10100	200	10000	200	10000	15374	12250	1	1	10201	100	99	2535	100	100	100	22832	22862	32781	0	24533	22761	10000	1	1	1	722	2	24	2	2	15342	10000	100	15379	15451	15504	15458	15392
10204	15414	115	329	173	328	24526	118	15432	9602	25	10100	100	10000	100	10000	500	724236	49	12430	15428	15413	13973	6	14110	10100	200	10000	200	10000	15411	12155	1	1	10201	100	99	2601	100	100	100	22760	22818	32794	0	24694	22712	10000	1	1	1	722	2	24	2	2	15259	10000	100	15338	15455	15467	15532	15469
10204	15382	115	331	176	326	24517	490	15452	9482	25	10100	100	10000	100	10000	500	724011	49	12409	15389	15376	14033	6	14078	10100	200	10000	200	10000	15349	12224	1	1	10201	100	99	2682	100	100	100	22840	22810	32847	1	24585	22793	10000	1	1	1	722	2	24	2	2	15319	10000	100	15376	15415	15429	15390	15424
10204	15518	115	325	173	327	24596	496	15470	9490	25	10100	100	10000	100	10000	500	721514	49	12352	15379	15446	14101	6	14214	10100	200	10000	200	10000	15380	12182	1	1	10201	100	99	2625	100	100	100	22739	22717	32806	1	24690	22917	10000	1	1	1	722	2	24	2	2	15328	10000	100	15511	15323	15486	15468	15425
10204	15475	115	327	173	327	24551	489	15373	9575	25	10100	100	10000	100	10000	500	720300	49	12228	15323	15453	13935	6	14123	10100	200	10000	200	10000	15383	12192	1	1	10201	100	99	2612	100	100	100	22756	22832	32653	1	24641	22873	10000	1	1	1	722	2	24	2	2	15292	10000	100	15381	15439	15467	15371	15379
10204	15367	116	329	168	325	24620	495	15456	9635	25	10100	100	10000	100	10000	500	721243	49	12309	15416	15435	13929	6	14179	10100	200	10000	200	10000	15351	12206	1	1	10201	100	99	2646	100	100	100	22855	22718	32805	0	24543	22801	10000	1	1	1	722	2	24	2	2	15331	10000	100	15428	15407	15360	15402	15453

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5471

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15514	120	0	363	183	356	0	24766	125	15480	9411	25	10010	10	10000	10	10000	50	725156	0	49	12383	15448	15374	14004	3	14187	10010	20	10000	20	10000	15395	15438	1	1	10021	10	9	2440	10	10	10	23079	22969	33009	0	24856	22926	10000	640	4	16	5	5	15364	10000	10	15496	15376	15456	15427	15450
10024	15494	115	0	368	195	364	0	24733	112	15427	9505	25	10010	10	10000	10	10000	50	726981	0	49	12381	15322	15477	14076	3	14176	10010	20	10000	20	10000	15390	15471	1	1	10021	10	9	2440	10	10	10	22991	23014	32956	0	24788	23013	10000	640	5	16	5	5	15381	10000	10	15550	15423	15431	15413	15487
10024	15419	116	0	365	189	366	0	24833	514	15424	9438	25	10010	10	10000	10	10000	50	724559	1	49	12332	15422	15467	14067	3	14238	10010	20	10000	20	10000	15428	15349	1	1	10021	10	9	2377	10	10	10	22866	22932	33004	0	24858	22931	10000	640	6	16	6	5	15289	10000	10	15383	15517	15464	15441	15457
10024	15583	119	0	367	185	364	0	24730	483	15448	9452	25	10010	10	10000	10	10000	50	723674	0	49	12378	15481	15442	13962	3	14241	10010	20	10000	20	10000	15421	15403	1	1	10021	10	9	2344	10	10	10	23070	22901	32937	0	24772	22951	10000	640	5	16	6	5	15387	10000	10	15358	15493	15500	15506	15445
10024	15466	116	0	365	194	372	0	24809	534	15504	9517	25	10010	10	10000	10	10000	50	727735	1	49	12399	15404	15457	14022	3	14191	10010	20	10000	20	10000	15366	15448	1	1	10021	10	9	2383	10	10	10	23004	22898	32911	0	24850	22907	10000	640	6	16	4	6	15343	10000	10	15471	15468	15517	15474	15506
10024	15375	115	0	368	192	367	0	24744	114	15405	9495	25	10010	10	10000	10	10000	50	724230	0	49	12375	15426	15519	14019	3	14248	10010	20	10000	20	10000	15408	15441	1	1	10021	10	9	2494	10	10	10	23030	22973	32979	0	24687	22979	10000	640	5	16	5	5	15458	10000	10	15441	15519	15462	15464	15473
10024	15448	115	0	367	197	371	0	24739	119	15467	9509	25	10010	10	10000	10	10000	50	721667	0	49	12342	15422	15498	14065	3	14187	10010	20	10000	20	10000	15395	15438	1	1	10021	10	9	2440	10	10	10	22997	23087	33018	1	24744	22942	10000	640	5	16	6	6	15374	10000	10	15409	15512	15414	15481	15429
10024	15473	116	0	369	192	367	0	24740	0	15419	9518	25	10010	10	10000	10	10000	50	721644	1	49	12344	15457	15428	14014	3	14191	10010	20	10000	20	10000	15483	15439	1	1	10021	10	9	2362	10	10	10	22933	22993	32998	0	24787	23059	10000	640	5	16	6	5	15398	10000	10	15464	15462	15485	15515	15713
10024	15425	116	0	363	193	374	0	24790	516	15401	9494	25	10010	10	10000	10	10000	50	722939	1	49	12323	15489	15489	14052	3	14245	10010	20	10000	20	10000	15439	15436	1	1	10021	10	9	2453	10	10	10	22926	22886	32980	1	24839	23034	10000	640	5	16	5	5	15356	10000	10	15427	15469	15440	15505	15419
10024	15473	116	0	371	199	362	0	24759	510	15438	9490	25	10010	10	10000	10	10000	50	724114	1	49	12359	15501	15501	14044	3	14203	10010	20	10000	20	10000	15413	15399	1	1	10021	10	9	2381	10	10	10	22931	22941	32939	1	24766	22989	10000	640	6	16	6	5	15265	10000	10	15401	15501	15490	15465	15517

PRFM (register, PLDL1KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations