Firestorm: NGC (register, 64-bit) measurements

Code:

  ngc x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	4	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	24	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62878	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	9	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	104	1	1	1001	1000	0	0	73	2	27	2	2	990	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  ngc x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	2	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	898	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	15	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10058
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	2	36	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	78	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10191	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	0	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	20200	10035	102	1	1	10201	100	99	100	10100	100	0	0	0	9	0	710	1	27	1	1	9992	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	11	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	45	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	141	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	104	1	1	10021	10	9	10	10010	10	0	9	640	2	27	2	2	9993	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Chain cycles: 1

Code:

  ngc x0, x1
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	61	19930	25	20200	20200	20212	1297733	0	49	16955	20035	20035	17425	7	17486	20212	20224	30236	20035	104	1	1	20201	100	99	20100	0	0	0	57	1	1	1	1320	0	16	0	0	20011	20122	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	57	61	19930	25	20200	20200	20212	1297733	1	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	104	1	1	20201	100	99	20100	0	0	0	18	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	104	1	1	20201	100	99	20100	0	0	5	3	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	104	1	1	20201	100	99	20100	0	2	27	3	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	104	1	1	20201	100	99	20100	0	0	2	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20067	17406	3	17481	20200	20200	30200	20035	104	1	1	20201	100	99	20100	0	0	23	51	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	104	1	1	20201	100	99	20100	0	0	6	6	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30200	20035	104	1	1	20201	100	99	20100	0	0	0	3	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	1	1	1	0	103	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17413	3	17481	20282	20200	30200	20035	104	1	1	20201	100	99	20100	0	0	0	6	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	30335	20035	104	1	1	20201	100	99	20100	0	0	24	72	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20068	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	25	3	1270	3	27	2	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	28	3	1270	3	27	3	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	26	0	1270	3	27	2	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	0	0	1270	2	27	2	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	2	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	0	0	1270	3	27	3	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	15	9	1270	3	27	3	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	0	0	1270	2	27	2	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	0	0	1270	3	27	3	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	1	0	0	1270	2	27	3	3	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	104	1	1	20021	10	9	20010	0	0	6	1270	3	27	3	4	19995	20010	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  ngc x0, x8
  ngc x1, x8
  ngc x2, x8
  ngc x3, x8
  ngc x4, x8
  ngc x5, x8
  ngc x6, x8
  ngc x7, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3343

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26740	200	0	0	693	27	80118	80118	80124	479916	1	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	29	0	1	1	1	5134	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	9	28	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	28	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	63	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	219	27	80118	80118	80124	479916	1	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	49	3	1	1	1	5118	0	16	0	0	26737	80018	80100	26774	26741	26741	26741	26741
80204	26740	200	0	0	28	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	1	9	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26788	201	0	0	28	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	0	6	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	28	27	80118	80118	80124	479916	1	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	1	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	1024	27	80118	80118	80124	479916	1	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	1	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	201	0	0	28	27	80118	80118	80124	479916	1	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	1	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741
80204	26740	200	0	0	503	27	80118	80118	80124	479916	0	49	23660	26740	26740	16679	6	16689	80124	80232	160264	26740	66	1	1	80201	100	99	100	80100	100	1	0	1	1	1	5118	0	16	0	0	26737	80018	80100	26741	26741	26741	26741	26741

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26722	200	0	0	0	0	0	0	78	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	7	18	4	3	26736	80000	80010	26892	26707	26707	26707	26849
80024	26706	201	0	0	0	0	0	0	363	46	80073	80010	80077	471051	0	49	23814	26751	26706	16690	3	16711	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	9	0	5020	3	18	3	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	136	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	6	0	5020	4	18	4	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	6	0	5020	4	18	3	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	78	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160168	26706	66	1	1	80021	10	9	10	80010	10	2	0	2	1	1	0	0	0	5020	4	27	4	4	26702	80067	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	3	0	5020	3	18	4	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26892	200	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	0	0	5020	3	18	4	3	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	12	0	36	25	80010	80010	80010	472059	1	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	3	0	5020	4	18	4	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	199	0	0	0	0	0	0	800	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	0	0	5020	3	18	3	4	26702	80000	80010	26707	26707	26707	26707	26707
80024	26706	200	0	0	0	0	0	0	36	25	80010	80010	80010	472059	0	49	23626	26706	26706	16665	3	16684	80010	80020	160020	26706	66	1	1	80021	10	9	10	80010	10	0	0	0	0	3	0	0	0	5020	3	18	3	4	26702	80000	80010	26707	26707	26707	26707	26707

NGC (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations