Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldp w0, w1, [x6, #8]!
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires: 3.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0f | 1e | 20 | 22 | 2b | 3a | 3e | 3f | 40 | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int load (95) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ab | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | c3 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 3005 | 1040 | 8 | 1 | 0 | 1 | 0 | 172 | 31 | 2 | 0 | 2 | 4 | 1025 | 12 | 8 | 1 | 0 | 18 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52855 | 45590 | 1 | 1045 | 1057 | 574 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1035 | 18 | 0 | 58 | 1031 | 3 | 0 | 14 | 12 | 27 | 1056 | 46 | 5 | 24 | 47 | 7 | 30 | 44 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 31 | 27 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 8 | 1 | 0 | 0 | 0 | 81 | 8 | 0 | 0 | 3 | 12 | 1025 | 0 | 8 | 0 | 2 | 11 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52834 | 45588 | 1 | 1040 | 1057 | 574 | 3 | 667 | 2000 | 1000 | 2000 | 1000 | 1000 | 1041 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1030 | 7 | 0 | 41 | 1034 | 1 | 0 | 19 | 4 | 34 | 1017 | 24 | 4 | 22 | 31 | 7 | 1 | 3 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 31 | 29 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 7 | 1 | 1 | 1 | 0 | 112 | 30 | 2 | 0 | 1 | 20 | 1025 | 16 | 8 | 0 | 3 | 16 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52858 | 45590 | 1 | 1040 | 1040 | 574 | 3 | 667 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1026 | 19 | 0 | 39 | 1025 | 0 | 0 | 38 | 12 | 28 | 1017 | 35 | 5 | 22 | 55 | 7 | 1 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 41 | 40 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 8 | 1 | 0 | 1 | 0 | 67 | 22 | 1 | 0 | 0 | 24 | 1025 | 10 | 8 | 0 | 0 | 13 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52837 | 45590 | 1 | 1040 | 1040 | 574 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1006 | 9 | 0 | 63 | 1027 | 0 | 0 | 1 | 0 | 38 | 1026 | 35 | 8 | 26 | 55 | 6 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 41 | 38 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 8 | 1 | 0 | 0 | 0 | 98 | 21 | 1 | 0 | 1 | 12 | 1044 | 0 | 8 | 2 | 14 | 20 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52831 | 45589 | 1 | 1040 | 1059 | 574 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1022 | 7 | 0 | 51 | 1061 | 2 | 0 | 21 | 6 | 29 | 1045 | 41 | 5 | 30 | 47 | 7 | 1 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 31 | 40 | 1000 | 2000 | 1046 | 1058 | 1058 | 1058 | 1041 |
| 3004 | 1040 | 8 | 1 | 0 | 1 | 0 | 98 | 22 | 0 | 0 | 1 | 0 | 1025 | 8 | 8 | 0 | 0 | 13 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52847 | 45591 | 1 | 1040 | 1040 | 574 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1025 | 6 | 0 | 51 | 1055 | 0 | 0 | 37 | 12 | 28 | 1038 | 41 | 6 | 34 | 47 | 7 | 43 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 29 | 29 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 8 | 1 | 1 | 1 | 0 | 62 | 0 | 0 | 0 | 2 | 20 | 1034 | 12 | 9 | 5 | 1 | 17 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52832 | 45592 | 1 | 1040 | 1040 | 574 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1020 | 8 | 0 | 51 | 1069 | 1 | 0 | 22 | 6 | 28 | 1031 | 42 | 6 | 28 | 55 | 7 | 1 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 37 | 32 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 8 | 1 | 1 | 1 | 0 | 94 | 23 | 0 | 0 | 1 | 0 | 1025 | 0 | 8 | 0 | 1 | 14 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52824 | 45590 | 1 | 1040 | 1040 | 575 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1056 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1009 | 7 | 0 | 55 | 1024 | 0 | 0 | 1 | 0 | 26 | 1017 | 30 | 6 | 26 | 47 | 7 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 33 | 38 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 7 | 1 | 0 | 1 | 0 | 113 | 15 | 0 | 0 | 3 | 0 | 1025 | 28 | 12 | 2 | 5 | 17 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52856 | 45590 | 1 | 1054 | 1057 | 574 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1026 | 7 | 0 | 59 | 1045 | 0 | 0 | 15 | 0 | 25 | 1018 | 24 | 6 | 32 | 63 | 7 | 1 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 35 | 24 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 3004 | 1040 | 8 | 1 | 0 | 1 | 0 | 106 | 24 | 1 | 0 | 2 | 12 | 1025 | 0 | 9 | 1 | 4 | 18 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 52854 | 45589 | 1 | 1040 | 1040 | 574 | 3 | 648 | 2000 | 1000 | 2000 | 1000 | 1000 | 1040 | 38 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1017 | 7 | 0 | 47 | 1055 | 2 | 0 | 12 | 12 | 23 | 1032 | 36 | 5 | 26 | 50 | 7 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 27 | 32 | 1000 | 2000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Chain cycles: 3
Code:
ldp w0, w1, [x6, #8]! eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.1755
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 43 | 49 | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ab | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | c3 | branch mispred nonspec (cb) | cf | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60209 | 72014 | 537 | 0 | 0 | 0 | 0 | 0 | 521 | 0 | 786 | 1 | 720 | 0 | 100 | 71738 | 777 | 1 | 2 | 71800 | 25 | 50735 | 40588 | 10130 | 40100 | 10000 | 617143 | 2739509 | 1 | 49 | 68654 | 71770 | 71692 | 63874 | 3 | 64181 | 50100 | 40200 | 20000 | 70200 | 10000 | 71737 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10918 | 1 | 152 | 490 | 10637 | 273 | 13 | 916 | 78 | 32 | 10955 | 111 | 2 | 130 | 0 | 0 | 3 | 0 | 2610 | 0 | 2 | 57 | 1 | 1 | 71452 | 40524 | 824 | 844 | 890 | 10000 | 50100 | 71807 | 72039 | 71760 | 71650 | 71649 |
| 60204 | 71796 | 537 | 0 | 0 | 0 | 0 | 0 | 583 | 0 | 833 | 1 | 760 | 0 | 72 | 71582 | 805 | 3 | 2 | 71497 | 25 | 50710 | 40620 | 10135 | 40100 | 10000 | 619170 | 2741569 | 1 | 49 | 68672 | 71722 | 71762 | 64025 | 3 | 64054 | 50100 | 40200 | 20000 | 70200 | 10000 | 71670 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10914 | 1 | 171 | 500 | 10632 | 277 | 12 | 902 | 112 | 35 | 10918 | 119 | 3 | 122 | 0 | 3 | 5 | 0 | 2610 | 0 | 1 | 58 | 1 | 1 | 71485 | 40500 | 830 | 894 | 894 | 10000 | 50100 | 71696 | 71989 | 71537 | 71635 | 71573 |
| 60204 | 71768 | 538 | 0 | 0 | 0 | 0 | 0 | 553 | 0 | 800 | 1 | 696 | 0 | 108 | 71656 | 804 | 2 | 2 | 71567 | 25 | 50790 | 40600 | 10139 | 40100 | 10000 | 616880 | 2744986 | 1 | 49 | 68734 | 71900 | 71760 | 63892 | 3 | 64051 | 50100 | 40200 | 20000 | 70200 | 10000 | 71612 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10904 | 1 | 162 | 547 | 10658 | 261 | 9 | 922 | 110 | 35 | 10926 | 133 | 3 | 134 | 0 | 0 | 3 | 0 | 2610 | 0 | 1 | 57 | 1 | 1 | 71584 | 40500 | 892 | 774 | 964 | 10000 | 50100 | 71671 | 71845 | 71801 | 71803 | 71622 |
| 60204 | 71709 | 537 | 0 | 0 | 0 | 0 | 0 | 597 | 0 | 818 | 1 | 696 | 0 | 104 | 71603 | 833 | 3 | 2 | 71525 | 25 | 50780 | 40612 | 10119 | 40100 | 10000 | 617571 | 2744620 | 0 | 49 | 68738 | 71751 | 71794 | 63880 | 3 | 64104 | 50100 | 40200 | 20000 | 70200 | 10000 | 71754 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10907 | 1 | 154 | 485 | 10641 | 279 | 11 | 933 | 44 | 46 | 10954 | 121 | 1 | 138 | 0 | 3 | 10 | 0 | 2610 | 0 | 1 | 57 | 1 | 1 | 71779 | 40524 | 798 | 862 | 852 | 10000 | 50100 | 71776 | 72070 | 71745 | 71840 | 71780 |
| 60204 | 71612 | 538 | 0 | 0 | 0 | 0 | 0 | 529 | 0 | 822 | 1 | 720 | 0 | 88 | 71584 | 827 | 3 | 2 | 71770 | 25 | 50690 | 40564 | 10122 | 40100 | 10000 | 617960 | 2739166 | 1 | 49 | 68568 | 71767 | 71717 | 63934 | 3 | 64201 | 50100 | 40200 | 20000 | 70200 | 10000 | 71907 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10900 | 1 | 153 | 482 | 10656 | 251 | 12 | 913 | 32 | 43 | 10910 | 120 | 2 | 137 | 0 | 0 | 8 | 0 | 2610 | 0 | 1 | 58 | 1 | 1 | 71643 | 40496 | 768 | 860 | 906 | 10000 | 50100 | 71644 | 71791 | 71767 | 71512 | 71598 |
| 60204 | 71775 | 539 | 0 | 0 | 0 | 0 | 0 | 591 | 0 | 825 | 1 | 728 | 0 | 124 | 71892 | 791 | 1 | 2 | 71763 | 25 | 50787 | 40600 | 10118 | 40100 | 10000 | 617707 | 2741667 | 1 | 49 | 68688 | 71799 | 71782 | 64051 | 3 | 64192 | 50100 | 40200 | 20000 | 70200 | 10000 | 71886 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10882 | 1 | 151 | 481 | 10642 | 230 | 11 | 890 | 50 | 36 | 10970 | 130 | 3 | 125 | 0 | 0 | 3 | 0 | 2610 | 0 | 1 | 58 | 1 | 1 | 71713 | 40480 | 844 | 904 | 866 | 10000 | 50100 | 71508 | 71744 | 71872 | 71583 | 71591 |
| 60204 | 71669 | 537 | 0 | 0 | 0 | 0 | 0 | 602 | 0 | 807 | 1 | 624 | 0 | 128 | 71649 | 799 | 3 | 2 | 71415 | 25 | 50780 | 40608 | 10119 | 40100 | 10000 | 617235 | 2735208 | 0 | 49 | 68635 | 71681 | 71794 | 63943 | 3 | 64108 | 50100 | 40200 | 20000 | 70200 | 10000 | 71808 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10915 | 1 | 164 | 473 | 10673 | 281 | 13 | 950 | 48 | 33 | 10894 | 118 | 2 | 129 | 0 | 0 | 9 | 0 | 2610 | 0 | 1 | 57 | 1 | 1 | 71517 | 40520 | 858 | 864 | 838 | 10000 | 50100 | 71697 | 71810 | 71669 | 71670 | 71688 |
| 60204 | 71810 | 536 | 0 | 0 | 0 | 0 | 0 | 561 | 0 | 838 | 1 | 704 | 0 | 148 | 71819 | 828 | 3 | 2 | 71399 | 25 | 50785 | 40572 | 10125 | 40100 | 10000 | 618229 | 2744568 | 1 | 49 | 68598 | 71741 | 71955 | 63791 | 3 | 63995 | 50100 | 40200 | 20000 | 70200 | 10000 | 71771 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10932 | 0 | 131 | 503 | 10662 | 287 | 14 | 919 | 78 | 38 | 10947 | 123 | 2 | 130 | 0 | 0 | 5 | 0 | 2610 | 0 | 1 | 58 | 1 | 1 | 71648 | 40472 | 836 | 952 | 854 | 10000 | 50100 | 71920 | 71925 | 71569 | 71753 | 71723 |
| 60204 | 71603 | 536 | 0 | 0 | 0 | 0 | 0 | 512 | 0 | 824 | 1 | 736 | 0 | 128 | 71654 | 795 | 2 | 3 | 71697 | 25 | 50745 | 40652 | 10132 | 40100 | 10000 | 617160 | 2738165 | 1 | 49 | 68679 | 71849 | 71860 | 63835 | 3 | 64170 | 50100 | 40200 | 20000 | 70200 | 10000 | 71898 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10904 | 0 | 138 | 487 | 10673 | 268 | 10 | 923 | 80 | 43 | 10952 | 129 | 3 | 135 | 0 | 0 | 3 | 0 | 2610 | 0 | 1 | 58 | 1 | 1 | 71738 | 40508 | 916 | 930 | 920 | 10000 | 50100 | 71617 | 71702 | 71758 | 71786 | 71565 |
| 60204 | 71551 | 536 | 0 | 0 | 0 | 0 | 0 | 613 | 88 | 802 | 1 | 728 | 0 | 112 | 71745 | 788 | 3 | 3 | 71527 | 25 | 50740 | 40588 | 10119 | 40100 | 10000 | 616099 | 2736145 | 1 | 49 | 68802 | 71770 | 71718 | 63899 | 3 | 64170 | 50100 | 40200 | 20000 | 70200 | 10000 | 71767 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10931 | 0 | 161 | 533 | 10643 | 247 | 10 | 906 | 60 | 33 | 10939 | 122 | 4 | 132 | 0 | 0 | 7 | 1 | 2610 | 0 | 1 | 57 | 1 | 1 | 71490 | 40472 | 924 | 896 | 940 | 10000 | 50100 | 71762 | 71914 | 71776 | 71747 | 71918 |
Result (median cycles for code, minus 3 chain cycles): 4.1731
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0f | 18 | 19 | 1e | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 43 | 49 | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ab | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | c3 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60029 | 72193 | 537 | 1 | 0 | 1 | 0 | 0 | 0 | 517 | 835 | 1 | 672 | 1 | 116 | 71810 | 801 | 2 | 0 | 71511 | 25 | 50575 | 40518 | 10127 | 40010 | 10000 | 617550 | 2741982 | 1 | 49 | 68705 | 71786 | 71678 | 63966 | 0 | 3 | 64160 | 50010 | 40020 | 20000 | 70020 | 10000 | 71738 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10896 | 1 | 141 | 532 | 10634 | 258 | 8 | 922 | 74 | 17 | 10908 | 140 | 3 | 121 | 1 | 1 | 9 | 0 | 2520 | 2 | 56 | 2 | 4 | 71503 | 40496 | 966 | 916 | 868 | 10000 | 50010 | 71875 | 71596 | 71707 | 71748 | 71809 |
| 60024 | 71644 | 537 | 1 | 0 | 0 | 0 | 0 | 0 | 542 | 803 | 1 | 712 | 1 | 100 | 71549 | 802 | 1 | 0 | 71489 | 25 | 50660 | 40498 | 10124 | 40010 | 10000 | 618468 | 2739151 | 1 | 49 | 68805 | 71770 | 71565 | 63924 | 7 | 3 | 64058 | 50010 | 40020 | 20000 | 70020 | 10000 | 71695 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10910 | 4 | 143 | 507 | 10641 | 276 | 8 | 931 | 104 | 113 | 10963 | 129 | 2 | 135 | 1 | 0 | 3 | 0 | 2520 | 3 | 56 | 2 | 4 | 71338 | 40504 | 950 | 1054 | 926 | 10000 | 50010 | 71852 | 71874 | 71828 | 71723 | 71657 |
| 60024 | 71711 | 537 | 1 | 0 | 0 | 0 | 0 | 0 | 549 | 852 | 1 | 720 | 2 | 136 | 71812 | 820 | 1 | 0 | 71389 | 25 | 50635 | 40538 | 10126 | 40010 | 10000 | 618621 | 2732546 | 0 | 49 | 68621 | 71881 | 71757 | 63995 | 0 | 3 | 64360 | 50010 | 40020 | 20000 | 70020 | 10000 | 71919 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10915 | 1 | 157 | 511 | 10635 | 262 | 8 | 915 | 44 | 23 | 10917 | 125 | 2 | 133 | 1 | 0 | 4 | 0 | 2520 | 4 | 56 | 5 | 4 | 71538 | 40468 | 968 | 794 | 952 | 10000 | 50010 | 71628 | 71555 | 71759 | 71797 | 71788 |
| 60024 | 71729 | 537 | 2 | 0 | 0 | 0 | 1 | 0 | 622 | 809 | 1 | 704 | 2 | 132 | 71688 | 797 | 1 | 0 | 71482 | 25 | 50665 | 40534 | 10129 | 40010 | 10000 | 618526 | 2742584 | 1 | 49 | 68590 | 71896 | 71648 | 64024 | 0 | 3 | 64309 | 50010 | 40020 | 20000 | 70020 | 10000 | 71727 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10910 | 2 | 151 | 489 | 10665 | 260 | 7 | 916 | 78 | 26 | 10945 | 126 | 2 | 142 | 1 | 0 | 7 | 0 | 2520 | 4 | 56 | 3 | 4 | 71603 | 40532 | 854 | 960 | 924 | 10000 | 50010 | 71688 | 71657 | 71712 | 71810 | 71838 |
| 60024 | 71963 | 539 | 1 | 0 | 0 | 0 | 0 | 0 | 509 | 802 | 1 | 576 | 1 | 108 | 71748 | 802 | 1 | 0 | 71439 | 25 | 50610 | 40534 | 10129 | 40010 | 10000 | 617964 | 2744623 | 0 | 49 | 68807 | 71680 | 71932 | 63907 | 0 | 3 | 64267 | 50010 | 40020 | 20000 | 70020 | 10000 | 71753 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10935 | 1 | 148 | 507 | 10656 | 258 | 8 | 923 | 78 | 29 | 10905 | 114 | 2 | 132 | 1 | 0 | 3 | 0 | 2520 | 3 | 56 | 2 | 4 | 71411 | 40464 | 938 | 806 | 964 | 10000 | 50010 | 71533 | 71769 | 71773 | 71804 | 71572 |
| 60024 | 71829 | 537 | 1 | 2 | 0 | 0 | 0 | 0 | 610 | 813 | 1 | 720 | 1 | 96 | 71738 | 777 | 1 | 0 | 71473 | 25 | 50675 | 40518 | 10126 | 40010 | 10000 | 618216 | 2736947 | 1 | 49 | 68510 | 71927 | 71663 | 63967 | 0 | 3 | 64145 | 50010 | 40020 | 20000 | 70020 | 10000 | 71664 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10845 | 2 | 165 | 456 | 10626 | 265 | 5 | 912 | 76 | 30 | 10933 | 123 | 2 | 138 | 1 | 3 | 9 | 0 | 2520 | 4 | 56 | 5 | 4 | 71438 | 40488 | 915 | 818 | 866 | 10000 | 50010 | 71721 | 71640 | 71722 | 71689 | 71718 |
| 60024 | 71797 | 536 | 1 | 0 | 0 | 0 | 0 | 0 | 526 | 844 | 1 | 736 | 1 | 96 | 71533 | 775 | 1 | 0 | 71655 | 25 | 50650 | 40542 | 10114 | 40010 | 10000 | 616524 | 2739126 | 1 | 49 | 68819 | 71791 | 71561 | 63882 | 0 | 3 | 64153 | 50010 | 40020 | 20000 | 70020 | 10000 | 71725 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10895 | 1 | 156 | 509 | 10649 | 269 | 8 | 970 | 80 | 23 | 10932 | 123 | 4 | 119 | 1 | 0 | 3 | 0 | 2520 | 4 | 56 | 4 | 2 | 71487 | 40468 | 972 | 872 | 988 | 10000 | 50010 | 71725 | 71850 | 71700 | 71740 | 71612 |
| 60024 | 71756 | 538 | 1 | 0 | 0 | 0 | 0 | 0 | 527 | 839 | 1 | 712 | 1 | 144 | 71838 | 784 | 2 | 0 | 71418 | 25 | 50600 | 40506 | 10113 | 40010 | 10000 | 616659 | 2740085 | 1 | 49 | 68405 | 71766 | 71707 | 63869 | 0 | 3 | 64156 | 50010 | 40020 | 20000 | 70020 | 10000 | 71774 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10898 | 10 | 140 | 502 | 10653 | 250 | 5 | 904 | 48 | 27 | 10950 | 118 | 3 | 138 | 2 | 0 | 9 | 0 | 2520 | 4 | 56 | 4 | 3 | 71395 | 40477 | 1050 | 928 | 860 | 10000 | 50010 | 71745 | 71700 | 71498 | 71656 | 71651 |
| 60024 | 71664 | 536 | 1 | 0 | 0 | 0 | 4 | 0 | 556 | 816 | 1 | 720 | 1 | 132 | 71605 | 823 | 0 | 0 | 71499 | 25 | 50665 | 40538 | 10120 | 40010 | 10000 | 619080 | 2737281 | 1 | 49 | 68830 | 71673 | 71739 | 63896 | 0 | 3 | 63974 | 50010 | 40020 | 20000 | 70020 | 10000 | 71797 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10976 | 1 | 148 | 497 | 10677 | 261 | 9 | 860 | 76 | 35 | 10919 | 124 | 2 | 136 | 1 | 3 | 1072 | 0 | 2520 | 3 | 56 | 2 | 4 | 71476 | 40484 | 910 | 862 | 864 | 10000 | 50010 | 71725 | 71754 | 71670 | 71621 | 71695 |
| 60024 | 71640 | 537 | 1 | 0 | 0 | 0 | 0 | 0 | 534 | 791 | 1 | 728 | 1 | 96 | 71897 | 809 | 1 | 0 | 71359 | 25 | 50590 | 40522 | 10126 | 40010 | 10000 | 616920 | 2741185 | 1 | 49 | 68941 | 71586 | 71646 | 63920 | 0 | 3 | 64312 | 50010 | 40020 | 20000 | 70020 | 10000 | 71712 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10935 | 1 | 147 | 493 | 10651 | 274 | 8 | 916 | 72 | 27 | 10888 | 124 | 3 | 130 | 1 | 3 | 13 | 0 | 2520 | 4 | 56 | 4 | 2 | 71466 | 40480 | 922 | 904 | 824 | 10000 | 50010 | 71775 | 71652 | 71787 | 71714 | 71556 |
Chain cycles: 3
Code:
ldp w0, w1, [x6, #8]! eor x8, x8, x1 eor x8, x8, x1 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.1863
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 43 | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9e | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ab | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | c3 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60209 | 72108 | 540 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 348 | 839 | 2 | 496 | 1 | 252 | 72006 | 791 | 0 | 71864 | 25 | 50780 | 40592 | 10132 | 40100 | 10000 | 618863 | 2742871 | 0 | 49 | 68781 | 71813 | 71913 | 63974 | 3 | 64316 | 50100 | 40200 | 20000 | 70200 | 10000 | 71756 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10917 | 1 | 154 | 498 | 10601 | 235 | 11 | 899 | 152 | 22 | 10879 | 126 | 1 | 119 | 1 | 0 | 11 | 0 | 0 | 2610 | 2 | 58 | 1 | 1 | 71556 | 40444 | 978 | 1092 | 1053 | 10000 | 50100 | 71815 | 71875 | 71840 | 71864 | 71888 |
| 60204 | 72039 | 538 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 379 | 845 | 2 | 528 | 1 | 236 | 71651 | 776 | 0 | 71683 | 25 | 50745 | 40600 | 10129 | 40100 | 10000 | 618680 | 2748480 | 1 | 49 | 68871 | 71844 | 71824 | 63947 | 33 | 64278 | 50100 | 40200 | 20000 | 70200 | 10000 | 71937 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10890 | 2 | 131 | 519 | 10618 | 260 | 9 | 886 | 120 | 28 | 10893 | 122 | 1 | 121 | 1 | 4 | 8 | 0 | 0 | 2610 | 1 | 56 | 1 | 1 | 71786 | 40488 | 1165 | 1080 | 1052 | 10000 | 50100 | 71974 | 71975 | 72036 | 72411 | 72242 |
| 60204 | 72178 | 542 | 1 | 2 | 0 | 0 | 0 | 0 | 4 | 5 | 1295 | 847 | 2 | 512 | 1 | 236 | 71957 | 801 | 0 | 71421 | 25 | 50755 | 40628 | 10129 | 40100 | 10000 | 616633 | 2753219 | 1 | 49 | 68884 | 71757 | 71811 | 63837 | 3 | 64522 | 50100 | 40200 | 20000 | 70200 | 10000 | 71712 | 35 | 3 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 1 | 100 | 10892 | 1 | 165 | 510 | 10704 | 256 | 7 | 868 | 130 | 31 | 10884 | 132 | 1 | 115 | 1 | 3 | 7 | 0 | 0 | 2610 | 1 | 57 | 1 | 1 | 71751 | 40500 | 957 | 1131 | 1068 | 10000 | 50100 | 71916 | 71813 | 71870 | 71883 | 71809 |
| 60204 | 71979 | 537 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 333 | 817 | 2 | 536 | 1 | 192 | 71925 | 787 | 0 | 71427 | 25 | 50680 | 40568 | 10125 | 40100 | 10000 | 616513 | 2742715 | 1 | 49 | 68593 | 71901 | 71832 | 63950 | 3 | 64210 | 50100 | 40200 | 20000 | 70200 | 10000 | 71833 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10892 | 1 | 157 | 531 | 10629 | 255 | 10 | 924 | 70 | 16 | 10908 | 118 | 1 | 112 | 1 | 0 | 10 | 0 | 0 | 2610 | 1 | 56 | 1 | 1 | 71584 | 40540 | 1069 | 990 | 1056 | 10000 | 50100 | 71824 | 71724 | 71906 | 71620 | 71865 |
| 60204 | 72138 | 538 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 385 | 805 | 2 | 504 | 1 | 224 | 71767 | 789 | 0 | 71637 | 25 | 50635 | 40596 | 10127 | 40100 | 10000 | 617963 | 2741604 | 1 | 49 | 68652 | 71843 | 71806 | 64005 | 3 | 64064 | 50100 | 40200 | 20000 | 70200 | 10000 | 71721 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10924 | 2 | 160 | 481 | 10701 | 236 | 12 | 884 | 120 | 28 | 10902 | 126 | 1 | 115 | 1 | 0 | 5 | 0 | 0 | 2610 | 1 | 58 | 1 | 1 | 71686 | 40468 | 1054 | 1017 | 985 | 10000 | 50100 | 71724 | 71806 | 71920 | 71838 | 71801 |
| 60204 | 71909 | 538 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 372 | 782 | 2 | 536 | 1 | 216 | 71833 | 821 | 0 | 71442 | 25 | 50700 | 40620 | 10110 | 40100 | 10000 | 619859 | 2750424 | 1 | 49 | 68619 | 71675 | 71822 | 64092 | 3 | 64511 | 50100 | 40200 | 20000 | 70200 | 10000 | 71813 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10902 | 2 | 159 | 519 | 10672 | 240 | 9 | 902 | 156 | 34 | 10912 | 129 | 1 | 114 | 1 | 0 | 11 | 0 | 0 | 2610 | 1 | 57 | 1 | 1 | 71826 | 40516 | 1126 | 1020 | 1034 | 10000 | 50100 | 71808 | 71563 | 71825 | 71908 | 71674 |
| 60204 | 71881 | 539 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 365 | 866 | 2 | 440 | 1 | 372 | 71784 | 783 | 0 | 71635 | 25 | 50725 | 40628 | 10120 | 40100 | 10000 | 618437 | 2738670 | 1 | 49 | 68737 | 71675 | 71925 | 63952 | 3 | 64186 | 50100 | 40200 | 20000 | 70200 | 10000 | 71977 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10899 | 2 | 145 | 596 | 10639 | 261 | 10 | 909 | 84 | 25 | 10903 | 136 | 1 | 123 | 1 | 0 | 7 | 0 | 0 | 2610 | 1 | 56 | 1 | 1 | 71595 | 40496 | 1078 | 1001 | 1076 | 10000 | 50100 | 71863 | 71959 | 71800 | 71849 | 71755 |
| 60204 | 71956 | 538 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 362 | 825 | 2 | 584 | 1 | 212 | 71731 | 775 | 0 | 71450 | 25 | 50680 | 40572 | 10126 | 40100 | 10000 | 618288 | 2739665 | 1 | 49 | 68721 | 71977 | 71712 | 64059 | 3 | 64129 | 50100 | 40200 | 20000 | 70200 | 10000 | 71781 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10913 | 1 | 136 | 528 | 10619 | 241 | 9 | 878 | 102 | 22 | 10891 | 133 | 1 | 130 | 1 | 15 | 14 | 0 | 0 | 2610 | 1 | 57 | 1 | 1 | 71591 | 40448 | 1041 | 1059 | 1050 | 10000 | 50100 | 71720 | 71741 | 71908 | 71810 | 71658 |
| 60204 | 71849 | 539 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 405 | 844 | 2 | 536 | 1 | 260 | 71679 | 782 | 0 | 71726 | 25 | 50710 | 40572 | 10129 | 40100 | 10000 | 617684 | 2741438 | 1 | 49 | 68623 | 71878 | 71810 | 64022 | 3 | 64209 | 50100 | 40200 | 20000 | 70200 | 10000 | 71895 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10909 | 3 | 140 | 484 | 10650 | 219 | 14 | 882 | 116 | 25 | 10906 | 130 | 1 | 129 | 1 | 1 | 11 | 0 | 0 | 2642 | 1 | 57 | 1 | 1 | 71647 | 40464 | 1043 | 991 | 1047 | 10000 | 50100 | 71760 | 71795 | 71764 | 72044 | 71822 |
| 60204 | 71748 | 538 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 380 | 863 | 2 | 528 | 1 | 280 | 71778 | 810 | 0 | 71628 | 25 | 50760 | 40560 | 10131 | 40100 | 10000 | 618966 | 2743184 | 1 | 49 | 68848 | 71770 | 71852 | 63891 | 3 | 64358 | 50100 | 40200 | 20000 | 70200 | 10000 | 72033 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 0 | 100 | 10918 | 1 | 129 | 509 | 10678 | 266 | 10 | 877 | 142 | 19 | 10900 | 134 | 1 | 133 | 1 | 2 | 6 | 0 | 0 | 2610 | 1 | 56 | 1 | 1 | 71609 | 40532 | 1038 | 1046 | 1019 | 10000 | 50100 | 71728 | 71884 | 72032 | 71868 | 71801 |
Result (median cycles for code, minus 3 chain cycles): 4.1850
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 43 | 49 | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 61 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9e | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ab | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | c3 | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 60029 | 71928 | 540 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 533 | 0 | 842 | 2 | 520 | 0 | 268 | 71781 | 801 | 3 | 2 | 71504 | 25 | 50685 | 40570 | 10138 | 40010 | 10000 | 619098 | 2745316 | 0 | 0 | 49 | 68905 | 0 | 71854 | 71864 | 63916 | 3 | 64235 | 50010 | 40020 | 20102 | 70020 | 10000 | 71640 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10916 | 1 | 148 | 519 | 10686 | 251 | 13 | 922 | 84 | 43 | 10938 | 140 | 3 | 132 | 1 | 0 | 21 | 2520 | 0 | 0 | 7 | 56 | 4 | 4 | 71644 | 40544 | 966 | 864 | 982 | 10000 | 50010 | 71860 | 71844 | 71864 | 72043 | 72099 |
| 60025 | 71872 | 538 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 538 | 0 | 855 | 2 | 384 | 2 | 200 | 71764 | 796 | 5 | 2 | 71635 | 25 | 50740 | 40542 | 10128 | 40010 | 10000 | 617766 | 2746366 | 0 | 0 | 49 | 68827 | 0 | 71891 | 71850 | 63955 | 3 | 64333 | 50010 | 40020 | 20000 | 70020 | 10000 | 71818 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10893 | 1 | 153 | 538 | 10651 | 285 | 16 | 922 | 130 | 45 | 10945 | 128 | 6 | 137 | 1 | 4 | 8 | 2520 | 5 | 0 | 5 | 56 | 4 | 4 | 71589 | 40520 | 940 | 960 | 942 | 10000 | 50010 | 71861 | 71941 | 71880 | 71889 | 71821 |
| 60024 | 71760 | 540 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 497 | 0 | 834 | 2 | 512 | 1 | 272 | 71834 | 823 | 3 | 2 | 71459 | 25 | 50660 | 40578 | 10128 | 40010 | 10000 | 618522 | 2749817 | 0 | 0 | 49 | 68852 | 0 | 71808 | 71808 | 63886 | 3 | 64288 | 50010 | 40020 | 20000 | 70020 | 10000 | 71900 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10909 | 1 | 153 | 516 | 10723 | 247 | 15 | 896 | 112 | 44 | 10942 | 132 | 3 | 142 | 1 | 0 | 3 | 2520 | 5 | 0 | 5 | 56 | 4 | 6 | 71581 | 40548 | 1016 | 936 | 966 | 10000 | 50010 | 71973 | 71803 | 71819 | 72003 | 71945 |
| 60024 | 71704 | 537 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 531 | 0 | 833 | 2 | 600 | 1 | 392 | 72032 | 815 | 3 | 2 | 71472 | 25 | 50650 | 40538 | 10137 | 40010 | 10000 | 619291 | 2754031 | 0 | 0 | 49 | 68799 | 0 | 71698 | 71894 | 64308 | 3 | 64249 | 50010 | 40020 | 20000 | 70020 | 10000 | 71849 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10923 | 1 | 143 | 502 | 10649 | 258 | 13 | 915 | 44 | 47 | 10939 | 124 | 4 | 122 | 1 | 0 | 6 | 2520 | 0 | 0 | 4 | 56 | 4 | 4 | 71733 | 40568 | 996 | 970 | 1014 | 10000 | 50010 | 71740 | 71992 | 71919 | 71840 | 71933 |
| 60024 | 71917 | 537 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 557 | 0 | 815 | 2 | 528 | 1 | 264 | 71843 | 835 | 5 | 2 | 71610 | 25 | 50680 | 40514 | 10134 | 40010 | 10000 | 618612 | 2744553 | 0 | 0 | 49 | 68865 | 0 | 71812 | 71732 | 64175 | 3 | 64312 | 50010 | 40020 | 20000 | 70020 | 10000 | 71830 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10950 | 3 | 137 | 489 | 10668 | 256 | 12 | 928 | 98 | 43 | 10930 | 124 | 5 | 130 | 1 | 6 | 8 | 2520 | 0 | 0 | 4 | 56 | 4 | 4 | 71585 | 40544 | 1012 | 1000 | 958 | 10000 | 50010 | 71785 | 71852 | 71919 | 71799 | 71792 |
| 60024 | 72004 | 540 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 534 | 0 | 851 | 2 | 504 | 1 | 280 | 71824 | 805 | 4 | 2 | 71397 | 25 | 50690 | 40614 | 10131 | 40010 | 10000 | 619642 | 2740791 | 0 | 0 | 49 | 68689 | 0 | 71868 | 71967 | 63944 | 3 | 64285 | 50010 | 40020 | 20000 | 70020 | 10000 | 71937 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10907 | 1 | 170 | 510 | 10647 | 263 | 13 | 928 | 166 | 48 | 10917 | 124 | 4 | 130 | 0 | 3 | 8 | 2520 | 0 | 0 | 4 | 56 | 4 | 4 | 71613 | 40560 | 996 | 984 | 1040 | 10000 | 50010 | 71778 | 71690 | 71897 | 71838 | 72148 |
| 60024 | 71787 | 538 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 513 | 0 | 841 | 2 | 560 | 2 | 216 | 71567 | 798 | 5 | 2 | 71740 | 25 | 50715 | 40562 | 10135 | 40010 | 10000 | 617892 | 2744088 | 0 | 0 | 49 | 69104 | 0 | 71820 | 71896 | 64102 | 3 | 64321 | 50010 | 40020 | 20000 | 70020 | 10000 | 71747 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10913 | 1 | 142 | 513 | 10695 | 248 | 15 | 907 | 114 | 43 | 10943 | 119 | 3 | 128 | 1 | 9 | 10 | 2520 | 0 | 0 | 4 | 56 | 5 | 4 | 71758 | 40544 | 882 | 952 | 932 | 10000 | 50010 | 71855 | 71722 | 71864 | 72067 | 71770 |
| 60024 | 71762 | 536 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 505 | 0 | 859 | 2 | 520 | 2 | 240 | 71915 | 804 | 5 | 2 | 71676 | 25 | 50800 | 40578 | 10148 | 40010 | 10000 | 618621 | 2745384 | 0 | 0 | 49 | 68639 | 0 | 71830 | 71866 | 64022 | 3 | 64289 | 50010 | 40020 | 20000 | 70020 | 10000 | 71905 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10919 | 2 | 131 | 528 | 10680 | 230 | 14 | 933 | 142 | 44 | 10934 | 135 | 4 | 138 | 0 | 18 | 19 | 2520 | 0 | 0 | 4 | 56 | 4 | 4 | 71644 | 40572 | 904 | 1046 | 928 | 10000 | 50010 | 71819 | 72035 | 71879 | 71955 | 71839 |
| 60024 | 71849 | 539 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 526 | 0 | 818 | 2 | 448 | 1 | 272 | 71466 | 817 | 3 | 3 | 71685 | 25 | 50720 | 40510 | 10136 | 40010 | 10000 | 619953 | 2744075 | 1 | 5 | 49 | 68851 | 0 | 71677 | 71851 | 63985 | 3 | 64138 | 50010 | 40186 | 20000 | 70020 | 10000 | 71752 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10901 | 2 | 136 | 527 | 10633 | 242 | 14 | 910 | 82 | 50 | 10925 | 123 | 5 | 128 | 1 | 0 | 21 | 2520 | 0 | 0 | 5 | 56 | 4 | 4 | 71598 | 40468 | 942 | 892 | 856 | 10000 | 50010 | 71884 | 71853 | 71700 | 71809 | 71847 |
| 60024 | 71655 | 538 | 1 | 0 | 0 | 0 | 0 | 0 | 3 | 539 | 0 | 869 | 2 | 504 | 1 | 340 | 71797 | 790 | 3 | 2 | 71574 | 25 | 50660 | 40598 | 10125 | 40010 | 10000 | 617748 | 2743465 | 0 | 0 | 49 | 68829 | 0 | 71880 | 71936 | 63929 | 3 | 64236 | 50010 | 40020 | 20000 | 70020 | 10000 | 71821 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 0 | 10 | 10907 | 1 | 141 | 525 | 10675 | 277 | 12 | 896 | 154 | 43 | 10902 | 140 | 6 | 146 | 1 | 10 | 4 | 2520 | 0 | 0 | 4 | 56 | 4 | 5 | 71682 | 40540 | 1026 | 968 | 836 | 10000 | 50010 | 71916 | 71840 | 71909 | 71847 | 72000 |
Count: 8
Code:
ldp w0, w1, [x6, #8]! ldp w0, w1, [x7, #8]! ldp w0, w1, [x8, #8]! ldp w0, w1, [x9, #8]! ldp w0, w1, [x10, #8]! ldp w0, w1, [x11, #8]! ldp w0, w1, [x12, #8]! ldp w0, w1, [x13, #8]!
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3965
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 1e | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 92 | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ab | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | c3 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 240209 | 32078 | 237 | 2 | 0 | 2 | 0 | 1 | 0 | 6771 | 827 | 1 | 728 | 130 | 144 | 31694 | 820 | 434 | 1736 | 1825 | 1647 | 29 | 160164 | 80137 | 80000 | 80118 | 80019 | 400645 | 690003 | 1 | 26 | 49 | 28751 | 31793 | 31733 | 1554 | 92 | 7 | 1595 | 160137 | 80218 | 160038 | 80218 | 80019 | 31673 | 38 | 1 | 1 | 80201 | 100 | 99 | 28 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80978 | 68 | 387 | 5654 | 85117 | 613 | 9 | 954 | 38 | 4981 | 85170 | 722 | 135 | 5034 | 5283 | 48 | 4 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 31634 | 31 | 80029 | 734 | 683 | 8 | 80000 | 160100 | 31761 | 31655 | 31694 | 31605 | 31791 |
| 240204 | 31690 | 237 | 3 | 3 | 2 | 0 | 0 | 2 | 6751 | 825 | 1 | 648 | 106 | 104 | 31693 | 780 | 494 | 1589 | 1593 | 1508 | 28 | 160157 | 80138 | 80013 | 80118 | 80019 | 400666 | 684030 | 0 | 20 | 49 | 28729 | 31676 | 31725 | 1686 | 104 | 3 | 1614 | 160100 | 80200 | 160000 | 80200 | 80000 | 31559 | 38 | 1 | 1 | 80201 | 100 | 99 | 32 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80978 | 49 | 363 | 5263 | 84995 | 660 | 11 | 902 | 104 | 5194 | 85627 | 842 | 126 | 5042 | 4987 | 48 | 5 | 7 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31759 | 31 | 80022 | 687 | 634 | 7 | 80000 | 160100 | 31556 | 31775 | 31789 | 31743 | 31925 |
| 240204 | 31860 | 238 | 3 | 0 | 3 | 0 | 0 | 1 | 6991 | 815 | 1 | 768 | 122 | 96 | 31685 | 799 | 496 | 1841 | 1949 | 1692 | 25 | 160122 | 80129 | 80000 | 80100 | 80000 | 400597 | 674862 | 0 | 20 | 49 | 28528 | 31635 | 31648 | 1521 | 58 | 3 | 1578 | 160100 | 80200 | 160000 | 80200 | 80000 | 31745 | 38 | 1 | 1 | 80201 | 100 | 99 | 18 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80954 | 51 | 380 | 5848 | 84889 | 615 | 13 | 914 | 48 | 4862 | 85972 | 860 | 120 | 5381 | 5331 | 32 | 3 | 3 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31936 | 24 | 80036 | 710 | 670 | 8 | 80000 | 160100 | 31719 | 31615 | 31743 | 31661 | 31741 |
| 240204 | 31648 | 237 | 3 | 0 | 0 | 1 | 1 | 0 | 6645 | 839 | 1 | 728 | 135 | 296 | 31698 | 798 | 523 | 2055 | 1936 | 1639 | 25 | 160126 | 80119 | 80000 | 80100 | 80000 | 400576 | 675328 | 1 | 21 | 49 | 28624 | 31564 | 31705 | 1779 | 107 | 3 | 1750 | 160100 | 80200 | 160000 | 80200 | 80000 | 31723 | 38 | 1 | 1 | 80201 | 100 | 99 | 40 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80936 | 49 | 372 | 5308 | 85559 | 632 | 12 | 911 | 70 | 5432 | 85460 | 828 | 129 | 5555 | 5975 | 50 | 3 | 4 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31648 | 32 | 80028 | 725 | 665 | 6 | 80000 | 160100 | 31644 | 31681 | 31676 | 31714 | 31843 |
| 240204 | 31806 | 238 | 3 | 2 | 0 | 0 | 0 | 1 | 7218 | 807 | 1 | 744 | 124 | 136 | 31672 | 783 | 517 | 1801 | 1929 | 1686 | 25 | 160128 | 80130 | 80000 | 80100 | 80000 | 400593 | 685170 | 0 | 28 | 49 | 28609 | 31742 | 31662 | 1664 | 51 | 3 | 1561 | 160100 | 80200 | 160000 | 80200 | 80000 | 31763 | 38 | 1 | 1 | 80201 | 100 | 99 | 20 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80978 | 48 | 394 | 5184 | 85414 | 660 | 9 | 926 | 68 | 5199 | 86246 | 828 | 129 | 4774 | 5441 | 50 | 3 | 3 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31666 | 33 | 80032 | 782 | 691 | 6 | 80000 | 160100 | 31705 | 31607 | 31684 | 31381 | 31587 |
| 240204 | 31719 | 238 | 3 | 0 | 0 | 0 | 0 | 0 | 7554 | 803 | 1 | 744 | 119 | 100 | 31671 | 785 | 525 | 1667 | 1898 | 1609 | 25 | 160135 | 80131 | 80000 | 80100 | 80000 | 400593 | 670323 | 0 | 28 | 49 | 28535 | 31889 | 31729 | 1633 | 120 | 3 | 1768 | 160100 | 80200 | 160000 | 80200 | 80000 | 31584 | 38 | 1 | 1 | 80201 | 100 | 99 | 36 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80954 | 32 | 392 | 5274 | 85330 | 641 | 12 | 879 | 54 | 4973 | 85952 | 716 | 129 | 5225 | 5206 | 32 | 4 | 5 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31757 | 33 | 80025 | 737 | 677 | 13 | 80000 | 160100 | 31668 | 31669 | 31675 | 31666 | 31592 |
| 240204 | 31765 | 238 | 2 | 1 | 0 | 0 | 1 | 0 | 6986 | 822 | 1 | 712 | 130 | 64 | 31534 | 805 | 535 | 1797 | 1530 | 1535 | 25 | 160121 | 80131 | 80000 | 80100 | 80000 | 400591 | 689487 | 0 | 26 | 49 | 28551 | 31654 | 31792 | 1663 | 69 | 3 | 1705 | 160100 | 80200 | 160000 | 80200 | 80000 | 31713 | 38 | 1 | 1 | 80201 | 100 | 99 | 22 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80936 | 51 | 338 | 4762 | 85486 | 601 | 11 | 934 | 36 | 4784 | 85698 | 805 | 134 | 5158 | 5428 | 32 | 3 | 7 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31757 | 30 | 80023 | 752 | 662 | 3 | 80000 | 160100 | 31666 | 31673 | 31828 | 31731 | 31720 |
| 240204 | 31578 | 237 | 3 | 0 | 1 | 1 | 0 | 0 | 7241 | 863 | 1 | 752 | 141 | 188 | 31816 | 792 | 489 | 1650 | 1750 | 1718 | 25 | 160135 | 80121 | 80000 | 80100 | 80000 | 400571 | 685930 | 1 | 19 | 49 | 28702 | 31665 | 31569 | 1464 | 44 | 3 | 1618 | 160100 | 80200 | 160000 | 80200 | 80000 | 31889 | 38 | 1 | 1 | 80201 | 100 | 99 | 22 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80918 | 31 | 382 | 5825 | 85374 | 620 | 9 | 918 | 50 | 5241 | 85658 | 769 | 130 | 5059 | 4939 | 34 | 1 | 3 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31851 | 34 | 80032 | 663 | 650 | 10 | 80000 | 160100 | 31744 | 31642 | 31524 | 31843 | 31725 |
| 240204 | 31648 | 238 | 2 | 0 | 0 | 0 | 1 | 0 | 6371 | 817 | 1 | 752 | 115 | 100 | 31642 | 775 | 466 | 1507 | 1689 | 1473 | 25 | 160128 | 80122 | 80000 | 80100 | 80000 | 400606 | 669387 | 0 | 23 | 49 | 28696 | 31547 | 31844 | 1542 | 59 | 3 | 1691 | 160100 | 80200 | 160000 | 80200 | 80000 | 31783 | 38 | 1 | 1 | 80201 | 100 | 99 | 22 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80942 | 47 | 395 | 5528 | 85254 | 653 | 10 | 927 | 76 | 4803 | 86365 | 726 | 117 | 5015 | 5584 | 48 | 6 | 3 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31691 | 29 | 80027 | 718 | 734 | 8 | 80000 | 160100 | 31730 | 31651 | 31631 | 31639 | 31756 |
| 240204 | 31912 | 239 | 3 | 3 | 3 | 3 | 0 | 0 | 6600 | 853 | 1 | 768 | 122 | 112 | 31942 | 829 | 458 | 1560 | 2200 | 1499 | 25 | 160133 | 80122 | 80000 | 80100 | 80000 | 400582 | 678909 | 1 | 26 | 49 | 28546 | 31689 | 31706 | 1595 | 48 | 3 | 1698 | 160100 | 80200 | 160000 | 80200 | 80000 | 31718 | 38 | 1 | 1 | 80201 | 100 | 99 | 25 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80911 | 35 | 378 | 5673 | 85182 | 672 | 12 | 884 | 52 | 5142 | 85518 | 781 | 128 | 5132 | 5635 | 32 | 8 | 3 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 31628 | 40 | 80027 | 691 | 705 | 12 | 80000 | 160100 | 31785 | 31807 | 31637 | 31784 | 31685 |
Result (median cycles for code divided by count): 0.3937
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 1e | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | 92 | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ab | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | c3 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 240029 | 31609 | 235 | 1 | 0 | 1 | 0 | 0 | 6865 | 816 | 1 | 712 | 99 | 144 | 31456 | 771 | 388 | 2076 | 2245 | 1347 | 25 | 160028 | 80032 | 80000 | 80010 | 80000 | 400117 | 660693 | 1 | 28 | 49 | 28403 | 0 | 31436 | 31419 | 1276 | 118 | 3 | 1429 | 160010 | 80020 | 160000 | 80020 | 80000 | 31417 | 38 | 1 | 1 | 80021 | 10 | 9 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80911 | 5 | 447 | 5661 | 84831 | 715 | 85 | 916 | 30 | 5057 | 85172 | 730 | 142 | 5127 | 4711 | 33 | 0 | 5 | 5020 | 5 | 16 | 6 | 6 | 31516 | 32 | 80026 | 403 | 455 | 5 | 80000 | 160010 | 31423 | 31471 | 31541 | 31446 | 31783 |
| 240024 | 31422 | 236 | 2 | 0 | 0 | 0 | 0 | 6299 | 808 | 1 | 744 | 89 | 132 | 31454 | 780 | 366 | 2089 | 2244 | 1301 | 25 | 160027 | 80037 | 80000 | 80010 | 80000 | 400126 | 640799 | 1 | 20 | 49 | 28388 | 0 | 31472 | 31499 | 1196 | 110 | 3 | 1414 | 160010 | 80020 | 160000 | 80020 | 80000 | 31269 | 38 | 1 | 1 | 80021 | 10 | 9 | 12 | 10 | 80000 | 10 | 80000 | 10 | 80916 | 16 | 407 | 5201 | 84930 | 749 | 68 | 888 | 68 | 5264 | 85703 | 772 | 101 | 4659 | 5213 | 32 | 2 | 5 | 5020 | 5 | 16 | 6 | 6 | 31575 | 29 | 80026 | 448 | 390 | 7 | 80000 | 160010 | 31468 | 31569 | 31326 | 31344 | 31740 |
| 240024 | 31394 | 237 | 2 | 0 | 1 | 0 | 0 | 7056 | 818 | 1 | 616 | 94 | 248 | 31651 | 840 | 355 | 2143 | 2027 | 1316 | 25 | 160034 | 80032 | 80000 | 80010 | 80000 | 400101 | 672145 | 1 | 24 | 49 | 28361 | 0 | 31754 | 31464 | 1149 | 187 | 3 | 1504 | 160010 | 80020 | 160000 | 80020 | 80000 | 31468 | 38 | 1 | 1 | 80021 | 10 | 9 | 11 | 10 | 80000 | 10 | 80000 | 10 | 80890 | 20 | 414 | 5527 | 85028 | 703 | 30 | 944 | 76 | 5832 | 85933 | 835 | 135 | 4976 | 5132 | 16 | 0 | 5 | 5020 | 6 | 16 | 5 | 5 | 31540 | 34 | 80025 | 450 | 426 | 5 | 80000 | 160010 | 31286 | 31437 | 31559 | 31294 | 31530 |
| 240024 | 31438 | 235 | 2 | 0 | 2 | 0 | 0 | 7004 | 796 | 1 | 672 | 93 | 124 | 31476 | 792 | 341 | 1940 | 2098 | 1386 | 25 | 160028 | 80030 | 80000 | 80010 | 80000 | 400135 | 677332 | 1 | 19 | 49 | 28341 | 0 | 31509 | 31484 | 1316 | 209 | 3 | 1383 | 160010 | 80020 | 160000 | 80020 | 80000 | 31591 | 38 | 1 | 1 | 80021 | 10 | 9 | 7 | 10 | 80000 | 10 | 80000 | 10 | 80927 | 49 | 392 | 5289 | 84975 | 745 | 30 | 956 | 46 | 5547 | 86316 | 798 | 115 | 5345 | 4983 | 49 | 0 | 5 | 5020 | 6 | 16 | 6 | 6 | 31488 | 32 | 80035 | 482 | 426 | 6 | 80000 | 160010 | 31437 | 31314 | 31515 | 31343 | 31686 |
| 240024 | 31774 | 236 | 3 | 0 | 0 | 0 | 0 | 6767 | 800 | 1 | 704 | 76 | 136 | 31451 | 780 | 336 | 2197 | 2238 | 1211 | 25 | 160034 | 80030 | 80000 | 80010 | 80000 | 400152 | 661067 | 0 | 22 | 49 | 28498 | 0 | 31509 | 31380 | 1276 | 175 | 3 | 1590 | 160010 | 80020 | 160000 | 80020 | 80000 | 31341 | 38 | 1 | 1 | 80021 | 10 | 9 | 11 | 10 | 80000 | 10 | 80000 | 10 | 80931 | 36 | 383 | 5779 | 84922 | 724 | 24 | 885 | 44 | 5444 | 86406 | 714 | 115 | 4881 | 4933 | 31 | 0 | 5 | 5020 | 4 | 15 | 6 | 7 | 31607 | 27 | 80015 | 442 | 397 | 4 | 80000 | 160010 | 31391 | 31461 | 31615 | 31320 | 31839 |
| 240024 | 31445 | 236 | 3 | 0 | 0 | 0 | 0 | 6835 | 795 | 1 | 664 | 82 | 120 | 31551 | 766 | 333 | 2043 | 2058 | 1115 | 25 | 160036 | 80036 | 80000 | 80010 | 80000 | 400150 | 650664 | 1 | 27 | 49 | 28410 | 0 | 31498 | 31435 | 1152 | 108 | 3 | 1568 | 160010 | 80020 | 160000 | 80020 | 80000 | 31438 | 38 | 1 | 1 | 80021 | 10 | 9 | 18 | 10 | 80000 | 10 | 80000 | 10 | 80908 | 48 | 406 | 5504 | 85300 | 725 | 52 | 923 | 28 | 4767 | 86276 | 752 | 124 | 5166 | 5139 | 47 | 3 | 7 | 5020 | 6 | 16 | 5 | 7 | 31431 | 31 | 80023 | 361 | 368 | 0 | 80000 | 160010 | 31273 | 31430 | 31490 | 31415 | 31699 |
| 240024 | 31425 | 236 | 3 | 0 | 0 | 0 | 0 | 6929 | 767 | 1 | 728 | 92 | 144 | 31472 | 763 | 386 | 1838 | 2197 | 1240 | 25 | 160031 | 80047 | 80000 | 80010 | 80000 | 400150 | 656625 | 1 | 31 | 49 | 28367 | 0 | 31434 | 31463 | 1259 | 115 | 3 | 1545 | 160010 | 80020 | 160000 | 80020 | 80000 | 31519 | 38 | 1 | 1 | 80021 | 10 | 9 | 16 | 10 | 80000 | 10 | 80000 | 10 | 80929 | 48 | 398 | 4935 | 85114 | 745 | 17 | 899 | 50 | 5345 | 86284 | 705 | 128 | 4484 | 4891 | 49 | 0 | 5 | 5020 | 4 | 15 | 4 | 5 | 31595 | 23 | 80017 | 507 | 387 | 7 | 80000 | 160010 | 31651 | 31453 | 31493 | 31422 | 31617 |
| 240024 | 31696 | 236 | 3 | 0 | 0 | 0 | 0 | 7674 | 827 | 1 | 672 | 87 | 232 | 31314 | 781 | 359 | 1967 | 1931 | 1332 | 25 | 160034 | 80046 | 80000 | 80010 | 80000 | 400123 | 671127 | 1 | 18 | 49 | 28350 | 0 | 31560 | 31698 | 1104 | 135 | 3 | 1290 | 160010 | 80020 | 160000 | 80020 | 80000 | 31608 | 38 | 1 | 1 | 80021 | 10 | 9 | 11 | 10 | 80000 | 10 | 80000 | 10 | 80903 | 48 | 388 | 4643 | 84878 | 721 | 25 | 948 | 50 | 4672 | 85545 | 753 | 125 | 4784 | 4870 | 51 | 0 | 7 | 5020 | 5 | 16 | 7 | 6 | 31484 | 22 | 80023 | 400 | 416 | 8 | 80000 | 160010 | 31572 | 31403 | 31524 | 31545 | 31848 |
| 240024 | 31491 | 236 | 3 | 0 | 2 | 0 | 0 | 6631 | 802 | 1 | 712 | 100 | 116 | 31377 | 787 | 353 | 2246 | 2069 | 1265 | 25 | 160031 | 80029 | 80000 | 80010 | 80000 | 400102 | 653943 | 1 | 28 | 49 | 28599 | 0 | 31497 | 31549 | 1229 | 143 | 3 | 1511 | 160010 | 80020 | 160000 | 80020 | 80000 | 31333 | 38 | 1 | 1 | 80021 | 10 | 9 | 12 | 10 | 80000 | 10 | 80000 | 10 | 80924 | 39 | 385 | 5166 | 84939 | 780 | 27 | 883 | 28 | 5090 | 85680 | 842 | 121 | 4884 | 4510 | 48 | 3 | 7 | 5020 | 7 | 16 | 5 | 7 | 31606 | 23 | 80022 | 367 | 388 | 0 | 80000 | 160010 | 31473 | 31423 | 31556 | 31210 | 31635 |
| 240024 | 31687 | 237 | 2 | 2 | 0 | 0 | 0 | 7210 | 802 | 1 | 528 | 89 | 132 | 31625 | 785 | 363 | 2062 | 2056 | 1359 | 25 | 160034 | 80037 | 80000 | 80010 | 80000 | 400119 | 675674 | 1 | 18 | 49 | 28272 | 0 | 31409 | 31564 | 1122 | 103 | 3 | 1446 | 160010 | 80020 | 160000 | 80020 | 80000 | 31514 | 38 | 1 | 1 | 80021 | 10 | 9 | 15 | 10 | 80000 | 10 | 80000 | 10 | 80937 | 49 | 370 | 5095 | 84680 | 727 | 16 | 939 | 44 | 5093 | 85844 | 770 | 127 | 5368 | 4923 | 47 | 4 | 2 | 5020 | 6 | 15 | 5 | 5 | 31321 | 31 | 80021 | 398 | 406 | 8 | 80000 | 160010 | 31354 | 31538 | 31575 | 31629 | 31833 |