Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (NSH)

Test 1: uops

Code:

  dsb nsh

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4151schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
1004170321280170170158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321270170170158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321280170170158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321280170170158011000100010006000149139521485917032316890100010001703217032111001100010000373116111683810001703317033170331703317033
1004170321270170170158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321280170170158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321270170170158011000100010006000049139521493317032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321270170170158011000100010006000149139521485917032316890100010001703217032111001100010001073116111683810001703317033170331703317033
1004170321270170170158011000100010006000049139521485917032316890100010001703217032111001100010001073116111683810001703317033170331703317033
100417032128117170170158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033

Test 2: throughput

Code:

  dsb nsh

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f414b51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1020417003212730000001700350015970010100100100001001000050059800049166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033
1020417003212730000001700170015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033
1020417003212730000001700170015970010100100100001001000050059800049166952151545170032316874010100200100002001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033
102041700321274000011101700170015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000010071011611169838010000100170033170033170033170033170033
1020417003212740000001700170015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033
1020417003212730000001700170015970010100100100001001000050059800149166952150935170032316874010100200100002001700321700511110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033
1020417003212740000001700170015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033
1020417003212740000001700170015970010100100100001001000050059800149166952150935170032316874010100200100412001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033
1020417003212730000001700170015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170056
1020417003212730000001700170015970010100100100001001000050059800149166952150935170032316874010100200100002001700321359191110201100991001001000010000010000000000071011611169838010000100170033170033170033170033170033

1000 unrolls and 10 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f4151schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
100241700321274000017001701597861001010100001010000505998014916695201500361700323168762100102010094201700321700471110021109101010000100100000006403163316983801000010170033170033170033170033170033
100241700321274000017001701597861001010100001010000505998004916695201499571700323168762100102010000201700321700321110021109101010000100100000006403162216983801000010170033170033170033170033170033
100241700321273000017001701599711002210100851010019505998004916699201499571700323168762100102010000201700321700321110021109101010000100100000006403162216983801000010170033170033170033170033170033
100241700321274000017001701597861001010100001010000505998004916695201499571700323168762100472010000201700321700321110021109101010000100100000006403163316983801000010170033170033170033170033170033
1002417003212730015017001701597861001010100001010000505998004916695201499571700323168762100102010000201700321700321110021109101010000100100000006403163316983801000010170033170033170033170033170033
10024170032127300501017001701597861001010100001010000505998004916695201499571700323168762100102010000201700321700321110021109101010000100100001006403163316983801000010170033170033170033170033170033
100241700321274001236017001701597861001010100001010000505998004916695201499571700323168762100102010000201700321700321110021109101010000100100001036403163316991401000010170033170033170033170033170033
100241700321273000017001701597861001010100001010000505998014916695201500271700323168762100102010000201700321700321110021109101010000100100000006403162216983801000010170033170033170033170033170033
1002417003212730012900170017015978610010101000010100005059980049166952014995717003217168762100102010000201700321700321110021109101010000100100000006403162216983801000010170033170033170033170033170033
10024170032127400930017001701597861001010100001010000505998014916695201499571700323168762100102010000201700321700321110021109101010000100100000006402163316983801000010170033170033170033170033170033